| Message ID | 20230208042850.1687-6-quic_kathirav@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [V2,1/5] clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types | expand |
On 2/8/2023 2:11 PM, Konrad Dybcio wrote: > > On 8.02.2023 05:28, Kathiravan T wrote: >> Add the APCS, A53 PLL, cpu-opp-table nodes to bump the CPU frequency >> above 800MHz. >> >> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> >> --- >> Changes in V2: >> - No changes >> >> arch/arm64/boot/dts/qcom/ipq5332.dtsi | 37 +++++++++++++++++++++++++++ >> 1 file changed, 37 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> index bdf33ef30e10..cec2828c51f8 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi >> @@ -5,6 +5,7 @@ >> * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> +#include <dt-bindings/clock/qcom,apss-ipq.h> >> #include <dt-bindings/clock/qcom,ipq5332-gcc.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> >> @@ -35,6 +36,8 @@ >> reg = <0x0>; >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >> + operating-points-v2 = <&cpu_opp_table>; >> }; >> >> CPU1: cpu@1 { >> @@ -43,6 +46,8 @@ >> reg = <0x1>; >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >> + operating-points-v2 = <&cpu_opp_table>; >> }; >> >> CPU2: cpu@2 { >> @@ -51,6 +56,8 @@ >> reg = <0x2>; >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >> + operating-points-v2 = <&cpu_opp_table>; >> }; >> >> CPU3: cpu@3 { >> @@ -59,6 +66,8 @@ >> reg = <0x3>; >> enable-method = "psci"; >> next-level-cache = <&L2_0>; >> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; >> + operating-points-v2 = <&cpu_opp_table>; >> }; >> >> L2_0: l2-cache { >> @@ -67,6 +76,16 @@ >> }; >> }; >> >> + cpu_opp_table: opp-table-cpu{ > opp-table-cpu { > + sort this properly (by node name, not label), please ahh, missed this. Will fix it in next spin. > >> + compatible = "operating-points-v2"; >> + opp-shared; >> + >> + opp-1488000000 { > Why only one (presumably FMAX) target? This sounds > very destructive to power consumption, and by extension > heat output. SKU is designed to operate on 1.48GHz only. > > The other changes generally look good fwiw. > > Konrad >> + opp-hz = /bits/ 64 <1488000000>; >> + clock-latency-ns = <200000>; >> + }; >> + }; >> + >> firmware { >> scm { >> compatible = "qcom,scm-ipq5332", "qcom,scm"; >> @@ -199,6 +218,24 @@ >> }; >> }; >> >> + apcs_glb: mailbox@b111000 { >> + compatible = "qcom,ipq5332-apcs-apps-global", >> + "qcom,ipq6018-apcs-apps-global"; >> + reg = <0x0b111000 0x1000>; >> + #clock-cells = <1>; >> + clocks = <&a53pll>, <&xo_board>; >> + clock-names = "pll", "xo"; >> + #mbox-cells = <1>; >> + }; >> + >> + a53pll: clock@b116000 { >> + compatible = "qcom,ipq5332-a53pll"; >> + reg = <0x0b116000 0x40>; >> + #clock-cells = <0>; >> + clocks = <&xo_board>; >> + clock-names = "xo"; >> + }; >> + >> timer@b120000 { >> compatible = "arm,armv7-timer-mem"; >> reg = <0x0b120000 0x1000>;
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index bdf33ef30e10..cec2828c51f8 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include <dt-bindings/clock/qcom,apss-ipq.h> #include <dt-bindings/clock/qcom,ipq5332-gcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -35,6 +36,8 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; CPU1: cpu@1 { @@ -43,6 +46,8 @@ reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; CPU2: cpu@2 { @@ -51,6 +56,8 @@ reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; CPU3: cpu@3 { @@ -59,6 +66,8 @@ reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; L2_0: l2-cache { @@ -67,6 +76,16 @@ }; }; + cpu_opp_table: opp-table-cpu{ + compatible = "operating-points-v2"; + opp-shared; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + clock-latency-ns = <200000>; + }; + }; + firmware { scm { compatible = "qcom,scm-ipq5332", "qcom,scm"; @@ -199,6 +218,24 @@ }; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq5332-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; + clocks = <&a53pll>, <&xo_board>; + clock-names = "pll", "xo"; + #mbox-cells = <1>; + }; + + a53pll: clock@b116000 { + compatible = "qcom,ipq5332-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>;
Add the APCS, A53 PLL, cpu-opp-table nodes to bump the CPU frequency above 800MHz. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> --- Changes in V2: - No changes arch/arm64/boot/dts/qcom/ipq5332.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)