diff mbox

[uboot,2/2] net: phy: ti: Allow the driver to be more configurable

Message ID 1459868722-6371-2-git-send-email-dmurphy@ti.com
State Superseded
Headers show

Commit Message

Dan Murphy April 5, 2016, 3:05 p.m. UTC 
Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree.  If the value is not set in the
devicetree then set the delay to the default.

If devicetree is not used then use the default defines within the
driver.

Signed-off-by: Dan Murphy <dmurphy@ti.com>

---

RFC->v1 - Added devicetree support - https://patchwork.ozlabs.org/patch/604113/

 drivers/net/phy/ti.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 73 insertions(+), 8 deletions(-)

-- 
2.8.0.rc3

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Comments

Dan Murphy April 5, 2016, 5:18 p.m. UTC | #1 
Michal

On 04/05/2016 12:01 PM, Michal Simek wrote:
> On 5.4.2016 17:05, Dan Murphy wrote:

>> Not all devices use the same internal delay or fifo depth.

>> Add the ability to set the internal delay for rx or tx and the

>> fifo depth via the devicetree.  If the value is not set in the

>> devicetree then set the delay to the default.

>>

>> If devicetree is not used then use the default defines within the

>> driver.

>>

>> Signed-off-by: Dan Murphy <dmurphy@ti.com>

>> ---

>>

>> RFC->v1 - Added devicetree support - https://patchwork.ozlabs.org/patch/604113/

>>

>>  drivers/net/phy/ti.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++------

>>  1 file changed, 73 insertions(+), 8 deletions(-)

>>

>> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c

>> index c3912d5..e91a6ed 100644

>> --- a/drivers/net/phy/ti.c

>> +++ b/drivers/net/phy/ti.c

>> @@ -6,6 +6,14 @@

>>   */

>>  #include <common.h>

>>  #include <phy.h>

>> +#include <linux/compat.h>

>> +#include <malloc.h>

>> +

>> +#include <fdtdec.h>

>> +#include <dm.h>

>> +#include <dt-bindings/net/ti-dp83867.h>

>> +

>> +DECLARE_GLOBAL_DATA_PTR;

>>  

>>  /* TI DP83867 */

>>  #define DP83867_DEVADDR		0x1f

>> @@ -57,6 +65,17 @@

>>  #define MII_MMD_CTRL_INCR_RDWT	0x8000 /* post increment on reads & writes */

>>  #define MII_MMD_CTRL_INCR_ON_WT	0xC000 /* post increment on writes only */

>>  

>> +/* User setting - can be taken from DTS */

>> +#define DEFAULT_RX_ID_DELAY	DP83867_RGMIIDCTL_2_25_NS

>> +#define DEFAULT_TX_ID_DELAY	DP83867_RGMIIDCTL_2_75_NS

>> +#define DEFAULT_FIFO_DEPTH	DP83867_PHYCR_FIFO_DEPTH_4_B_NIB

>> +

>> +struct dp83867_private {

>> +	int rx_id_delay;

>> +	int tx_id_delay;

>> +	int fifo_depth;

>> +};

>> +

>>  /**

>>   * phy_read_mmd_indirect - reads data from the MMD registers

>>   * @phydev: The PHY device bus

>> @@ -134,16 +153,58 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev)

>>  		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;

>>  }

>>  

>> -/* User setting - can be taken from DTS */

>> -#define RX_ID_DELAY	8

>> -#define TX_ID_DELAY	0xa

>> -#define FIFO_DEPTH	1

>> +#if defined(CONFIG_DM_ETH)

>> +/**

>> + * dp83867_data_init - Convenience function for setting PHY specific data

>> + *

>> + * @phydev: the phy_device struct

>> + */

>> +static int dp83867_of_init(struct phy_device *phydev)

>> +{

>> +	struct dp83867_private *dp83867 = phydev->priv;

>> +	struct udevice *dev = phydev->dev;

>> +

>> +	dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,

>> +				 "ti,rx_int_delay", DEFAULT_RX_ID_DELAY);

>> +

>> +	dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,

>> +				 "ti,tx_int_delay", DEFAULT_TX_ID_DELAY);

>> +

> this is not aligned with the binding you sent.

> ti,rx-internal-delay

> and

> ti,tx-internal-delay


You are right I will fix it and then make the same change in the kernel

Dan

>

>

> Thanks,

> Michal



-- 
------------------
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Dan Murphy April 5, 2016, 6:30 p.m. UTC | #2 
On 04/05/2016 12:36 PM, Michal Simek wrote:
> On 5.4.2016 19:18, Dan Murphy wrote:

>> Michal

>>

>> On 04/05/2016 12:01 PM, Michal Simek wrote:

>>> On 5.4.2016 17:05, Dan Murphy wrote:

>>>> Not all devices use the same internal delay or fifo depth.

>>>> Add the ability to set the internal delay for rx or tx and the

>>>> fifo depth via the devicetree.  If the value is not set in the

>>>> devicetree then set the delay to the default.

>>>>

>>>> If devicetree is not used then use the default defines within the

>>>> driver.

>>>>

>>>> Signed-off-by: Dan Murphy <dmurphy@ti.com>

>>>> ---

>>>>

>>>> RFC->v1 - Added devicetree support - https://patchwork.ozlabs.org/patch/604113/

>>>>

>>>>  drivers/net/phy/ti.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++------

>>>>  1 file changed, 73 insertions(+), 8 deletions(-)

>>>>

>>>> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c

>>>> index c3912d5..e91a6ed 100644

>>>> --- a/drivers/net/phy/ti.c

>>>> +++ b/drivers/net/phy/ti.c

>>>> @@ -6,6 +6,14 @@

>>>>   */

>>>>  #include <common.h>

>>>>  #include <phy.h>

>>>> +#include <linux/compat.h>

>>>> +#include <malloc.h>

>>>> +

>>>> +#include <fdtdec.h>

>>>> +#include <dm.h>

>>>> +#include <dt-bindings/net/ti-dp83867.h>

>>>> +

>>>> +DECLARE_GLOBAL_DATA_PTR;

>>>>  

>>>>  /* TI DP83867 */

>>>>  #define DP83867_DEVADDR		0x1f

>>>> @@ -57,6 +65,17 @@

>>>>  #define MII_MMD_CTRL_INCR_RDWT	0x8000 /* post increment on reads & writes */

>>>>  #define MII_MMD_CTRL_INCR_ON_WT	0xC000 /* post increment on writes only */

>>>>  

>>>> +/* User setting - can be taken from DTS */

>>>> +#define DEFAULT_RX_ID_DELAY	DP83867_RGMIIDCTL_2_25_NS

>>>> +#define DEFAULT_TX_ID_DELAY	DP83867_RGMIIDCTL_2_75_NS

>>>> +#define DEFAULT_FIFO_DEPTH	DP83867_PHYCR_FIFO_DEPTH_4_B_NIB

>>>> +

>>>> +struct dp83867_private {

>>>> +	int rx_id_delay;

>>>> +	int tx_id_delay;

>>>> +	int fifo_depth;

>>>> +};

>>>> +

>>>>  /**

>>>>   * phy_read_mmd_indirect - reads data from the MMD registers

>>>>   * @phydev: The PHY device bus

>>>> @@ -134,16 +153,58 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev)

>>>>  		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;

>>>>  }

>>>>  

>>>> -/* User setting - can be taken from DTS */

>>>> -#define RX_ID_DELAY	8

>>>> -#define TX_ID_DELAY	0xa

>>>> -#define FIFO_DEPTH	1

>>>> +#if defined(CONFIG_DM_ETH)

>>>> +/**

>>>> + * dp83867_data_init - Convenience function for setting PHY specific data

>>>> + *

>>>> + * @phydev: the phy_device struct

>>>> + */

>>>> +static int dp83867_of_init(struct phy_device *phydev)

>>>> +{

>>>> +	struct dp83867_private *dp83867 = phydev->priv;

>>>> +	struct udevice *dev = phydev->dev;

>>>> +

>>>> +	dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,

>>>> +				 "ti,rx_int_delay", DEFAULT_RX_ID_DELAY);

>>>> +

>>>> +	dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,

>>>> +				 "ti,tx_int_delay", DEFAULT_TX_ID_DELAY);

>>>> +

>>> this is not aligned with the binding you sent.

>>> ti,rx-internal-delay

>>> and

>>> ti,tx-internal-delay

>> You are right I will fix it and then make the same change in the kernel

> Why not just follow linux binding?

> Changing binding in kernel will end up in deprecated binding for nothing.


What specific Linux binding are you referring to?

I don't see this binding getting changed as the internal delay and fifo depth
are board configurable options and I don't for see the register map changing for this
device.

Dan


> Thanks,

> Michal

>

>



-- 
------------------
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Dan Murphy April 5, 2016, 6:45 p.m. UTC | #3 
On 04/05/2016 01:30 PM, Dan Murphy wrote:
> On 04/05/2016 12:36 PM, Michal Simek wrote:

>> On 5.4.2016 19:18, Dan Murphy wrote:

>>> Michal

>>>

>>> On 04/05/2016 12:01 PM, Michal Simek wrote:

>>>> On 5.4.2016 17:05, Dan Murphy wrote:

>>>>> Not all devices use the same internal delay or fifo depth.

>>>>> Add the ability to set the internal delay for rx or tx and the

>>>>> fifo depth via the devicetree.  If the value is not set in the

>>>>> devicetree then set the delay to the default.

>>>>>

>>>>> If devicetree is not used then use the default defines within the

>>>>> driver.

>>>>>

>>>>> Signed-off-by: Dan Murphy <dmurphy@ti.com>

>>>>> ---

>>>>>

>>>>> RFC->v1 - Added devicetree support - https://patchwork.ozlabs.org/patch/604113/

>>>>>

>>>>>  drivers/net/phy/ti.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++------

>>>>>  1 file changed, 73 insertions(+), 8 deletions(-)

>>>>>

>>>>> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c

>>>>> index c3912d5..e91a6ed 100644

>>>>> --- a/drivers/net/phy/ti.c

>>>>> +++ b/drivers/net/phy/ti.c

>>>>> @@ -6,6 +6,14 @@

>>>>>   */

>>>>>  #include <common.h>

>>>>>  #include <phy.h>

>>>>> +#include <linux/compat.h>

>>>>> +#include <malloc.h>

>>>>> +

>>>>> +#include <fdtdec.h>

>>>>> +#include <dm.h>

>>>>> +#include <dt-bindings/net/ti-dp83867.h>

>>>>> +

>>>>> +DECLARE_GLOBAL_DATA_PTR;

>>>>>  

>>>>>  /* TI DP83867 */

>>>>>  #define DP83867_DEVADDR		0x1f

>>>>> @@ -57,6 +65,17 @@

>>>>>  #define MII_MMD_CTRL_INCR_RDWT	0x8000 /* post increment on reads & writes */

>>>>>  #define MII_MMD_CTRL_INCR_ON_WT	0xC000 /* post increment on writes only */

>>>>>  

>>>>> +/* User setting - can be taken from DTS */

>>>>> +#define DEFAULT_RX_ID_DELAY	DP83867_RGMIIDCTL_2_25_NS

>>>>> +#define DEFAULT_TX_ID_DELAY	DP83867_RGMIIDCTL_2_75_NS

>>>>> +#define DEFAULT_FIFO_DEPTH	DP83867_PHYCR_FIFO_DEPTH_4_B_NIB

>>>>> +

>>>>> +struct dp83867_private {

>>>>> +	int rx_id_delay;

>>>>> +	int tx_id_delay;

>>>>> +	int fifo_depth;

>>>>> +};

>>>>> +

>>>>>  /**

>>>>>   * phy_read_mmd_indirect - reads data from the MMD registers

>>>>>   * @phydev: The PHY device bus

>>>>> @@ -134,16 +153,58 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev)

>>>>>  		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;

>>>>>  }

>>>>>  

>>>>> -/* User setting - can be taken from DTS */

>>>>> -#define RX_ID_DELAY	8

>>>>> -#define TX_ID_DELAY	0xa

>>>>> -#define FIFO_DEPTH	1

>>>>> +#if defined(CONFIG_DM_ETH)

>>>>> +/**

>>>>> + * dp83867_data_init - Convenience function for setting PHY specific data

>>>>> + *

>>>>> + * @phydev: the phy_device struct

>>>>> + */

>>>>> +static int dp83867_of_init(struct phy_device *phydev)

>>>>> +{

>>>>> +	struct dp83867_private *dp83867 = phydev->priv;

>>>>> +	struct udevice *dev = phydev->dev;

>>>>> +

>>>>> +	dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,

>>>>> +				 "ti,rx_int_delay", DEFAULT_RX_ID_DELAY);

>>>>> +

>>>>> +	dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,

>>>>> +				 "ti,tx_int_delay", DEFAULT_TX_ID_DELAY);

>>>>> +

>>>> this is not aligned with the binding you sent.

>>>> ti,rx-internal-delay

>>>> and

>>>> ti,tx-internal-delay

>>> You are right I will fix it and then make the same change in the kernel

>> Why not just follow linux binding?

>> Changing binding in kernel will end up in deprecated binding for nothing.

> What specific Linux binding are you referring to?

>

> I don't see this binding getting changed as the internal delay and fifo depth

> are board configurable options and I don't for see the register map changing for this

> device.


I see it now.  Will submit v3 of the driver but I will wait for additional comments
before sending tomorrow.


Dan

> Dan

>

>

>> Thanks,

>> Michal

>>

>>

>



-- 
------------------
Dan Murphy

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diff mbox

Patch

diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index c3912d5..e91a6ed 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -6,6 +6,14 @@ 
  */
 #include <common.h>
 #include <phy.h>
+#include <linux/compat.h>
+#include <malloc.h>
+
+#include <fdtdec.h>
+#include <dm.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* TI DP83867 */
 #define DP83867_DEVADDR		0x1f
@@ -57,6 +65,17 @@ 
 #define MII_MMD_CTRL_INCR_RDWT	0x8000 /* post increment on reads & writes */
 #define MII_MMD_CTRL_INCR_ON_WT	0xC000 /* post increment on writes only */
 
+/* User setting - can be taken from DTS */
+#define DEFAULT_RX_ID_DELAY	DP83867_RGMIIDCTL_2_25_NS
+#define DEFAULT_TX_ID_DELAY	DP83867_RGMIIDCTL_2_75_NS
+#define DEFAULT_FIFO_DEPTH	DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
+
+struct dp83867_private {
+	int rx_id_delay;
+	int tx_id_delay;
+	int fifo_depth;
+};
+
 /**
  * phy_read_mmd_indirect - reads data from the MMD registers
  * @phydev: The PHY device bus
@@ -134,16 +153,58 @@  static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
 		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
 }
 
-/* User setting - can be taken from DTS */
-#define RX_ID_DELAY	8
-#define TX_ID_DELAY	0xa
-#define FIFO_DEPTH	1
+#if defined(CONFIG_DM_ETH)
+/**
+ * dp83867_data_init - Convenience function for setting PHY specific data
+ *
+ * @phydev: the phy_device struct
+ */
+static int dp83867_of_init(struct phy_device *phydev)
+{
+	struct dp83867_private *dp83867 = phydev->priv;
+	struct udevice *dev = phydev->dev;
+
+	dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,rx_int_delay", DEFAULT_RX_ID_DELAY);
+
+	dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,tx_int_delay", DEFAULT_TX_ID_DELAY);
+
+	dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,fifo_depth", DEFAULT_FIFO_DEPTH);
+
+	return 0;
+}
+#else
+static int dp83867_of_init(struct phy_device *phydev)
+{
+	dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
+	dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
+	dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
+
+	return 0;
+}
+#endif
 
 static int dp83867_config(struct phy_device *phydev)
 {
+	struct dp83867_private *dp83867;
 	unsigned int val, delay;
 	int ret;
 
+	if (!phydev->priv) {
+		dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
+		if (!dp83867)
+			return -ENOMEM;
+
+		phydev->priv = dp83867;
+		ret = dp83867_of_init(phydev);
+		if (ret)
+			goto err_out;
+	} else {
+		dp83867 = (struct dp83867_private *)phydev->priv;
+	}
+
 	/* Restart the PHY.  */
 	val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 	phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
@@ -152,9 +213,9 @@  static int dp83867_config(struct phy_device *phydev)
 	if (phy_interface_is_rgmii(phydev)) {
 		ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 			(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
-			(FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 		if (ret)
-			return ret;
+			goto err_out;
 	}
 
 	if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
@@ -175,8 +236,8 @@  static int dp83867_config(struct phy_device *phydev)
 		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 				       DP83867_DEVADDR, phydev->addr, val);
 
-		delay = (RX_ID_DELAY |
-			 (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+		delay = (dp83867->rx_id_delay |
+			 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 
 		phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 				       DP83867_DEVADDR, phydev->addr, delay);
@@ -184,6 +245,10 @@  static int dp83867_config(struct phy_device *phydev)
 
 	genphy_config_aneg(phydev);
 	return 0;
+
+err_out:
+	kfree(dp83867);
+	return ret;
 }
 
 static struct phy_driver DP83867_driver = {