diff mbox series

[3/5] hw/ppc/ppc4xx: Set QDev properties using QDev API

Message ID 20230203211623.50930-4-philmd@linaro.org
State New
Headers show
Series hw/ppc: Set QDev properties using QDev API (part 2/3) | expand

Commit Message

Philippe Mathieu-Daudé Feb. 3, 2023, 9:16 p.m. UTC 
No need to use the low-level QOM API when an object
inherits from QDev. Directly use the QDev API to set
its properties.

All calls use either errp=&error_abort or &error_fatal,
so converting to the QDev API is almost a no-op (QDev
API always uses &error_abort).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/ppc/e500.c          | 3 +--
 hw/ppc/ppc405_boards.c | 6 ++----
 hw/ppc/ppc405_uc.c     | 6 +++---
 hw/ppc/ppc440_bamboo.c | 3 +--
 hw/ppc/ppc4xx_devs.c   | 2 +-
 hw/ppc/sam460ex.c      | 5 ++---
 6 files changed, 10 insertions(+), 15 deletions(-)

Comments

BALATON Zoltan Feb. 3, 2023, 9:26 p.m. UTC | #1 
On Fri, 3 Feb 2023, Philippe Mathieu-Daudé wrote:
> No need to use the low-level QOM API when an object
> inherits from QDev. Directly use the QDev API to set
> its properties.
>
> All calls use either errp=&error_abort or &error_fatal,
> so converting to the QDev API is almost a no-op (QDev
> API always uses &error_abort).
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>

> ---
> hw/ppc/e500.c          | 3 +--
> hw/ppc/ppc405_boards.c | 6 ++----
> hw/ppc/ppc405_uc.c     | 6 +++---
> hw/ppc/ppc440_bamboo.c | 3 +--
> hw/ppc/ppc4xx_devs.c   | 2 +-
> hw/ppc/sam460ex.c      | 5 ++---
> 6 files changed, 10 insertions(+), 15 deletions(-)
>
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index 9fa1f8e6cf..083961cef5 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -943,8 +943,7 @@ void ppce500_init(MachineState *machine)
>          * Secondary CPU starts in halted state for now. Needs to change
>          * when implementing non-kernel boot.
>          */
> -        object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0,
> -                                 &error_fatal);
> +        qdev_prop_set_bit(DEVICE(cs), "start-powered-off", i != 0);
>         qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal);
>
>         if (!firstenv) {
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 4092ebc1ab..67eb9ac139 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -276,10 +276,8 @@ static void ppc405_init(MachineState *machine)
>
>     object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
>                             TYPE_PPC405_SOC);
> -    object_property_set_link(OBJECT(&ppc405->soc), "dram",
> -                             OBJECT(machine->ram), &error_abort);
> -    object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
> -                             &error_abort);
> +    qdev_prop_set_link(DEVICE(&ppc405->soc), "dram", OBJECT(machine->ram));
> +    qdev_prop_set_uint32(DEVICE(&ppc405->soc), "sys-clk", 33333333);
>     qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>
>     /* allocate and load BIOS */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index c973cfb04e..b7d5cfc548 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1080,7 +1080,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>      * We use the 440 DDR SDRAM controller which has more regs and features
>      * but it's compatible enough for now
>      */
> -    object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
> +    qdev_prop_set_uint32(DEVICE(&s->sdram), "nbanks", 2);
>     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
>         return;
>     }
> @@ -1147,8 +1147,8 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>     }
>
>     /* MAL */
> -    object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
> -    object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
> +    qdev_prop_set_uint8(DEVICE(&s->mal), "txc-num", 4);
> +    qdev_prop_set_uint8(DEVICE(&s->mal), "rxc-num", 2);
>     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) {
>         return;
>     }
> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
> index 81d71adf34..3612471990 100644
> --- a/hw/ppc/ppc440_bamboo.c
> +++ b/hw/ppc/ppc440_bamboo.c
> @@ -200,8 +200,7 @@ static void bamboo_init(MachineState *machine)
>
>     /* SDRAM controller */
>     dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR);
> -    object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
> -                             &error_abort);
> +    qdev_prop_set_link(dev, "dram", OBJECT(machine->ram));
>     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
>     object_unref(OBJECT(dev));
>     /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index c1d111465d..1848cf5d3c 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -535,7 +535,7 @@ void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
> bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
>                         Error **errp)
> {
> -    object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
> +    qdev_prop_set_link(DEVICE(dev), "cpu", OBJECT(cpu));
>     return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
> }
>
> diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
> index cf065aae0e..cb828b6d4d 100644
> --- a/hw/ppc/sam460ex.c
> +++ b/hw/ppc/sam460ex.c
> @@ -345,13 +345,12 @@ static void sam460ex_init(MachineState *machine)
>         exit(1);
>     }
>     dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2);
> -    object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
> -                             &error_abort);
> +    qdev_prop_set_link(dev, "dram", OBJECT(machine->ram));
>     /*
>      * Put all RAM on first bank because board has one slot
>      * and firmware only checks that
>      */
> -    object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort);
> +    qdev_prop_set_uint32(dev, "nbanks", 1);
>     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
>     object_unref(OBJECT(dev));
>     /* FIXME: does 460EX have ECC interrupts? */
>
Daniel Henrique Barboza Feb. 5, 2023, 10:59 a.m. UTC | #2 
On 2/3/23 18:16, Philippe Mathieu-Daudé wrote:
> No need to use the low-level QOM API when an object
> inherits from QDev. Directly use the QDev API to set
> its properties.
> 
> All calls use either errp=&error_abort or &error_fatal,
> so converting to the QDev API is almost a no-op (QDev
> API always uses &error_abort).
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>

>   hw/ppc/e500.c          | 3 +--
>   hw/ppc/ppc405_boards.c | 6 ++----
>   hw/ppc/ppc405_uc.c     | 6 +++---
>   hw/ppc/ppc440_bamboo.c | 3 +--
>   hw/ppc/ppc4xx_devs.c   | 2 +-
>   hw/ppc/sam460ex.c      | 5 ++---
>   6 files changed, 10 insertions(+), 15 deletions(-)
> 
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index 9fa1f8e6cf..083961cef5 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -943,8 +943,7 @@ void ppce500_init(MachineState *machine)
>            * Secondary CPU starts in halted state for now. Needs to change
>            * when implementing non-kernel boot.
>            */
> -        object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0,
> -                                 &error_fatal);
> +        qdev_prop_set_bit(DEVICE(cs), "start-powered-off", i != 0);
>           qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal);
>   
>           if (!firstenv) {
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 4092ebc1ab..67eb9ac139 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -276,10 +276,8 @@ static void ppc405_init(MachineState *machine)
>   
>       object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
>                               TYPE_PPC405_SOC);
> -    object_property_set_link(OBJECT(&ppc405->soc), "dram",
> -                             OBJECT(machine->ram), &error_abort);
> -    object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
> -                             &error_abort);
> +    qdev_prop_set_link(DEVICE(&ppc405->soc), "dram", OBJECT(machine->ram));
> +    qdev_prop_set_uint32(DEVICE(&ppc405->soc), "sys-clk", 33333333);
>       qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>   
>       /* allocate and load BIOS */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index c973cfb04e..b7d5cfc548 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1080,7 +1080,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>        * We use the 440 DDR SDRAM controller which has more regs and features
>        * but it's compatible enough for now
>        */
> -    object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
> +    qdev_prop_set_uint32(DEVICE(&s->sdram), "nbanks", 2);
>       if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
>           return;
>       }
> @@ -1147,8 +1147,8 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>       }
>   
>       /* MAL */
> -    object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
> -    object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
> +    qdev_prop_set_uint8(DEVICE(&s->mal), "txc-num", 4);
> +    qdev_prop_set_uint8(DEVICE(&s->mal), "rxc-num", 2);
>       if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) {
>           return;
>       }
> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
> index 81d71adf34..3612471990 100644
> --- a/hw/ppc/ppc440_bamboo.c
> +++ b/hw/ppc/ppc440_bamboo.c
> @@ -200,8 +200,7 @@ static void bamboo_init(MachineState *machine)
>   
>       /* SDRAM controller */
>       dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR);
> -    object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
> -                             &error_abort);
> +    qdev_prop_set_link(dev, "dram", OBJECT(machine->ram));
>       ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
>       object_unref(OBJECT(dev));
>       /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index c1d111465d..1848cf5d3c 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -535,7 +535,7 @@ void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
>   bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
>                           Error **errp)
>   {
> -    object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
> +    qdev_prop_set_link(DEVICE(dev), "cpu", OBJECT(cpu));
>       return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
>   }
>   
> diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
> index cf065aae0e..cb828b6d4d 100644
> --- a/hw/ppc/sam460ex.c
> +++ b/hw/ppc/sam460ex.c
> @@ -345,13 +345,12 @@ static void sam460ex_init(MachineState *machine)
>           exit(1);
>       }
>       dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2);
> -    object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
> -                             &error_abort);
> +    qdev_prop_set_link(dev, "dram", OBJECT(machine->ram));
>       /*
>        * Put all RAM on first bank because board has one slot
>        * and firmware only checks that
>        */
> -    object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort);
> +    qdev_prop_set_uint32(dev, "nbanks", 1);
>       ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
>       object_unref(OBJECT(dev));
>       /* FIXME: does 460EX have ECC interrupts? */
diff mbox series

Patch

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 9fa1f8e6cf..083961cef5 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -943,8 +943,7 @@  void ppce500_init(MachineState *machine)
          * Secondary CPU starts in halted state for now. Needs to change
          * when implementing non-kernel boot.
          */
-        object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0,
-                                 &error_fatal);
+        qdev_prop_set_bit(DEVICE(cs), "start-powered-off", i != 0);
         qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal);
 
         if (!firstenv) {
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 4092ebc1ab..67eb9ac139 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -276,10 +276,8 @@  static void ppc405_init(MachineState *machine)
 
     object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
                             TYPE_PPC405_SOC);
-    object_property_set_link(OBJECT(&ppc405->soc), "dram",
-                             OBJECT(machine->ram), &error_abort);
-    object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
-                             &error_abort);
+    qdev_prop_set_link(DEVICE(&ppc405->soc), "dram", OBJECT(machine->ram));
+    qdev_prop_set_uint32(DEVICE(&ppc405->soc), "sys-clk", 33333333);
     qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
 
     /* allocate and load BIOS */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index c973cfb04e..b7d5cfc548 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1080,7 +1080,7 @@  static void ppc405_soc_realize(DeviceState *dev, Error **errp)
      * We use the 440 DDR SDRAM controller which has more regs and features
      * but it's compatible enough for now
      */
-    object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
+    qdev_prop_set_uint32(DEVICE(&s->sdram), "nbanks", 2);
     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
         return;
     }
@@ -1147,8 +1147,8 @@  static void ppc405_soc_realize(DeviceState *dev, Error **errp)
     }
 
     /* MAL */
-    object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
-    object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
+    qdev_prop_set_uint8(DEVICE(&s->mal), "txc-num", 4);
+    qdev_prop_set_uint8(DEVICE(&s->mal), "rxc-num", 2);
     if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) {
         return;
     }
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 81d71adf34..3612471990 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -200,8 +200,7 @@  static void bamboo_init(MachineState *machine)
 
     /* SDRAM controller */
     dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR);
-    object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
-                             &error_abort);
+    qdev_prop_set_link(dev, "dram", OBJECT(machine->ram));
     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
     object_unref(OBJECT(dev));
     /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index c1d111465d..1848cf5d3c 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -535,7 +535,7 @@  void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
                         Error **errp)
 {
-    object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+    qdev_prop_set_link(DEVICE(dev), "cpu", OBJECT(cpu));
     return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
 }
 
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index cf065aae0e..cb828b6d4d 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -345,13 +345,12 @@  static void sam460ex_init(MachineState *machine)
         exit(1);
     }
     dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2);
-    object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
-                             &error_abort);
+    qdev_prop_set_link(dev, "dram", OBJECT(machine->ram));
     /*
      * Put all RAM on first bank because board has one slot
      * and firmware only checks that
      */
-    object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort);
+    qdev_prop_set_uint32(dev, "nbanks", 1);
     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
     object_unref(OBJECT(dev));
     /* FIXME: does 460EX have ECC interrupts? */