diff mbox series

arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node

Message ID 20230127174014.251539-1-prabhakar.mahadev-lad.rj@bp.renesas.com
State New
Headers show
Series arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node | expand

Commit Message

Lad, Prabhakar Jan. 27, 2023, 5:40 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable the performance monitor unit for the Cortex-A55 cores on the
RZ/G2L (r9a07g044) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Krzysztof Kozlowski Jan. 27, 2023, 5:54 p.m. UTC | #1 
On 27/01/2023 18:40, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Enable the performance monitor unit for the Cortex-A55 cores on the
> RZ/G2L (r9a07g044) SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> index 80b2332798d9..ff9bdc03a3ed 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -161,6 +161,11 @@ opp-50000000 {
>  		};
>  	};
>  
> +	pmu_a55 {

No underscores in node names. This is usually called just 'pmu'.

Best regards,
Krzysztof
Biju Das Jan. 27, 2023, 6:38 p.m. UTC | #2 
Hi Prabhakar,

Thanks for the patch.

> Subject: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Enable the performance monitor unit for the Cortex-A55 cores on the RZ/G2L
> (r9a07g044) SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> index 80b2332798d9..ff9bdc03a3ed 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -161,6 +161,11 @@ opp-50000000 {
>  		};
>  	};
> 
> +	pmu_a55 {
> +		compatible = "arm,cortex-a55-pmu";
> +		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;

Just a question, Is it tested? timer node[1] defines irq type as LOW, here it is high.
Also do we need to define (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW) as it has 2 cores??

[1]
timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

Cheers,
Biju


> +	};
> +
>  	psci {
>  		compatible = "arm,psci-1.0", "arm,psci-0.2";
>  		method = "smc";
> --
> 2.25.1
Lad, Prabhakar Jan. 27, 2023, 8:44 p.m. UTC | #3 
Hi Biju,

Thank you for the review.

On Fri, Jan 27, 2023 at 6:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > Subject: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable the performance monitor unit for the Cortex-A55 cores on the RZ/G2L
> > (r9a07g044) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > index 80b2332798d9..ff9bdc03a3ed 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > @@ -161,6 +161,11 @@ opp-50000000 {
> >               };
> >       };
> >
> > +     pmu_a55 {
> > +             compatible = "arm,cortex-a55-pmu";
> > +             interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>
> Just a question, Is it tested?
Yes this was tested with perf test (https://pastebin.com/dkckcYHr)

> timer node[1] defines irq type as LOW, here it is high.
You are right looking at the RZG2L_InterruptMapping_rev01.xlsx this
should be LOW. (I followed the SPI IRQS where all the LEVEL interrupts
are HIGH)

> Also do we need to define (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW) as it has 2 cores??
>
No this is not required for example here [0] where it has 6 cores.

[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r8a779f0.dtsi?h=v6.2-rc5#n203

Cheers,
Prabhakar
Biju Das Jan. 27, 2023, 9:48 p.m. UTC | #4 
Hi Prabhakar,


> Subject: Re: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node
> 
> Hi Biju,
> 
> Thank you for the review.
> 
> On Fri, Jan 27, 2023 at 6:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > Subject: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU
> > > node
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Enable the performance monitor unit for the Cortex-A55 cores on the
> > > RZ/G2L
> > > (r9a07g044) SoC.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > >  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > index 80b2332798d9..ff9bdc03a3ed 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > @@ -161,6 +161,11 @@ opp-50000000 {
> > >               };
> > >       };
> > >
> > > +     pmu_a55 {
> > > +             compatible = "arm,cortex-a55-pmu";
> > > +             interrupts-extended = <&gic GIC_PPI 7
> > > + IRQ_TYPE_LEVEL_HIGH>;
> >
> > Just a question, Is it tested?
> Yes this was tested with perf test
> 
> > timer node[1] defines irq type as LOW, here it is high.
> You are right looking at the RZG2L_InterruptMapping_rev01.xlsx this should
> be LOW. (I followed the SPI IRQS where all the LEVEL interrupts are HIGH)
> 
> > Also do we need to define (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW) as
> it has 2 cores??
> >
> No this is not required for example here [0] where it has 6 cores.

I may be wrong, That is the only example[1], where the A55 PMU per cpu interrupts and number of a55 cores in the DT 
are not matching.

[1]
https://elixir.bootlin.com/linux/latest/B/ident/arm%2Ccortex-a55-pmu

Cheers,
Biju
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 80b2332798d9..ff9bdc03a3ed 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -161,6 +161,11 @@  opp-50000000 {
 		};
 	};
 
+	pmu_a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	psci {
 		compatible = "arm,psci-1.0", "arm,psci-0.2";
 		method = "smc";