@@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B
bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
select CPU_V7
+config ARCH_UNIPHIER_LD20
+ bool "UniPhier PH1-LD20 SoC"
+ select ARM64
+ select SPL_SEPARATE_BSS
+
endchoice
config ARCH_UNIPHIER_LD4
@@ -31,3 +31,4 @@ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
obj-$(CONFIG_CPU_V7) += arm32/
+obj-$(CONFIG_ARM64) += arm64/
new file mode 100644
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj- += dummy.o
+ifndef CONFIG_SPL_BUILD
+obj-y += mem_map.o
+endif
new file mode 100644
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region uniphier_mem_map[] = {
+ {
+ .base = 0x00000000,
+ .size = 0x80000000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ .base = 0x80000000,
+ .size = 0xc0000000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ { /* sentinel */ }
+};
+
+struct mm_region *mem_map = uniphier_mem_map;
@@ -36,7 +36,7 @@ struct uniphier_fdt_file {
static const struct uniphier_fdt_file uniphier_fdt_files[] = {
{ "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
{ "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
- { "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
+ { "socionext,ph1-ld20-ref", "uniphier-ph1-ld20-ref.dtb", },
{ "socionext,ph1-pro4-ace", "uniphier-ph1-pro4-ace.dtb", },
{ "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
{ "socionext,ph1-pro4-sanji", "uniphier-ph1-pro4-sanji.dtb", },
@@ -165,6 +165,28 @@ static const struct uniphier_board_data ph1_ld6b_data = {
};
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+static const struct uniphier_board_data uniphier_ld20_data = {
+ .dram_freq = 1866,
+ .dram_nr_ch = 3,
+ .dram_ch[0] = {
+ .base = 0x80000000,
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .dram_ch[1] = {
+ .base = 0xc0000000,
+ .size = 0x40000000,
+ .width = 32,
+ },
+ .dram_ch[2] = {
+ .base = 0x100000000UL,
+ .size = 0x40000000,
+ .width = 32,
+ },
+};
+#endif
+
struct uniphier_board_id {
const char *compatible;
const struct uniphier_board_data *param;
@@ -194,6 +216,9 @@ static const struct uniphier_board_id uniphier_boards[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{ "socionext,ph1-ld6b", &ph1_ld6b_data, },
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+ { "socionext,ph1-ld20", &uniphier_ld20_data, },
+#endif
};
const struct uniphier_board_data *uniphier_get_board_param(void)
@@ -11,5 +11,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
@@ -16,11 +16,13 @@ u32 ph1_sld3_boot_device(void);
u32 ph1_ld4_boot_device(void);
u32 ph1_pro5_boot_device(void);
u32 proxstream2_boot_device(void);
+u32 uniphier_ld20_boot_device(void);
void ph1_sld3_boot_mode_show(void);
void ph1_ld4_boot_mode_show(void);
void ph1_pro5_boot_mode_show(void);
void proxstream2_boot_mode_show(void);
+void uniphier_ld20_boot_mode_show(void);
u32 spl_boot_device_raw(void);
new file mode 100644
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+
+#include "../sg-regs.h"
+#include "boot-device.h"
+
+static struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 5)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"},
+ {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
+ {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
+ {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+};
+
+static int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 uniphier_ld20_boot_device(void)
+{
+ int boot_mode;
+
+ if (~readl(SG_PINMON0) & 0x00000780)
+ return BOOT_DEVICE_USB;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void uniphier_ld20_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
@@ -39,6 +39,10 @@ u32 spl_boot_device_raw(void)
case SOC_UNIPHIER_LD6B:
return proxstream2_boot_device();
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+ case SOC_UNIPHIER_LD20:
+ return uniphier_ld20_boot_device();
+#endif
default:
return BOOT_DEVICE_NONE;
}
@@ -39,6 +39,11 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
proxstream2_boot_mode_show();
break;
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+ case SOC_UNIPHIER_LD20:
+ uniphier_ld20_boot_mode_show();
+ break;
+#endif
default:
break;
}
@@ -48,7 +48,7 @@ int print_cpuinfo(void)
puts("PH1-LD11 ()");
break;
case 0x32:
- puts("PH1-LD20 ()");
+ puts("PH1-LD20 (SC1401AJ1)");
break;
default:
printf("Unknown Processor ID (0x%x)\n", revision);
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \
ddrphy-training.o ddrphy-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
else
new file mode 100644
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+
+int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o
new file mode 100644
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "../init.h"
+
+int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
@@ -32,6 +32,7 @@ int ph1_pro4_init(const struct uniphier_board_data *bd);
int ph1_sld8_init(const struct uniphier_board_data *bd);
int ph1_pro5_init(const struct uniphier_board_data *bd);
int proxstream2_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD)
int sbc_admulti_init(const struct uniphier_board_data *bd);
@@ -91,6 +92,7 @@ int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
int proxstream2_umc_init(const struct uniphier_board_data *bd);
+int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
void ph1_sld3_pin_init(void);
void ph1_ld4_pin_init(void);
@@ -11,3 +11,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += init-sld8.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o
new file mode 100644
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_ld20_init(const struct uniphier_board_data *bd)
+{
+ sbc_savepin_init(bd);
+
+ support_card_reset();
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+ proxstream2_memconf_init(bd);
+
+ led_puts("L1");
+
+ uniphier_ld20_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = uniphier_ld20_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ led_puts("L6");
+
+ return 0;
+}
@@ -55,6 +55,11 @@ void spl_board_init(void)
proxstream2_init(param);
break;
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+ case SOC_UNIPHIER_LD20:
+ uniphier_ld20_init(param);
+ break;
+#endif
default:
break;
}
@@ -6,3 +6,4 @@ obj-y += memconf.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += memconf-sld3.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += memconf-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += memconf-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += memconf-pxs2.o
@@ -49,6 +49,9 @@ int proxstream2_memconf_init(const struct uniphier_board_data *bd)
case SZ_512M:
tmp |= SG_MEMCONF_CH2_SZ_512M;
break;
+ case SZ_1G:
+ tmp |= SG_MEMCONF_CH2_SZ_1G;
+ break;
default:
pr_err("error: unsupported DRAM Ch2 size\n");
return -EINVAL;
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o
obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o
obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o
@@ -50,10 +50,11 @@
#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16))
#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
-/* PH1-LD6b, ProXstream2 only */
+/* PH1-LD6b, ProXstream2, PH1-LD20 only */
#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
new file mode 100644
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_LD20=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_MMC_UNIPHIER=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_STORAGE=y
@@ -77,8 +77,7 @@
/* serial console configuration */
#define CONFIG_BAUDRATE 115200
-
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif
@@ -105,8 +104,16 @@
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
+#ifdef CONFIG_ARM64
+#define COUNTER_FREQUENCY 50000000
+#define CONFIG_GICV3
+#define GICD_BASE 0x5fe00000
+#define GICR_BASE 0x5fe80000
+#else
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE 1000000
+#endif
+
/*
* By default, ARP timeout is 5 sec.
@@ -252,14 +259,21 @@
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_NR_DRAM_BANKS 2
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || defined(CONFIG_ARCH_UNIPHIER_LD4) || \
+#if defined(CONFIG_ARM64)
+#define CONFIG_SPL_TEXT_BASE 0x30000000
+#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
+ defined(CONFIG_ARCH_UNIPHIER_LD4) || \
defined(CONFIG_ARCH_UNIPHIER_SLD8)
#define CONFIG_SPL_TEXT_BASE 0x00040000
#else
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#define CONFIG_SPL_STACK (0x3001c000)
+#else
#define CONFIG_SPL_STACK (0x00100000)
+#endif
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
#define CONFIG_PANIC_HANG
@@ -267,8 +281,10 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NOR_SUPPORT
+#ifndef CONFIG_ARM64
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
+#endif
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
#define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -284,5 +300,7 @@
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_BSS_START_ADDR 0x30016000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- arch/arm/mach-uniphier/Kconfig | 5 ++ arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/arm64/Makefile | 8 +++ arch/arm/mach-uniphier/arm64/mem_map.c | 28 +++++++++ arch/arm/mach-uniphier/board_late_init.c | 2 +- arch/arm/mach-uniphier/boards.c | 25 ++++++++ arch/arm/mach-uniphier/boot-mode/Makefile | 1 + arch/arm/mach-uniphier/boot-mode/boot-device.h | 2 + arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c | 77 +++++++++++++++++++++++ arch/arm/mach-uniphier/boot-mode/boot-mode.c | 4 ++ arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c | 5 ++ arch/arm/mach-uniphier/cpu_info.c | 2 +- arch/arm/mach-uniphier/dram/Makefile | 1 + arch/arm/mach-uniphier/dram/umc-ld20.c | 14 +++++ arch/arm/mach-uniphier/early-clk/Makefile | 1 + arch/arm/mach-uniphier/early-clk/early-clk-ld20.c | 12 ++++ arch/arm/mach-uniphier/init.h | 2 + arch/arm/mach-uniphier/init/Makefile | 1 + arch/arm/mach-uniphier/init/init-ld20.c | 55 ++++++++++++++++ arch/arm/mach-uniphier/init/init.c | 5 ++ arch/arm/mach-uniphier/memconf/Makefile | 1 + arch/arm/mach-uniphier/memconf/memconf-pxs2.c | 3 + arch/arm/mach-uniphier/sbc/Makefile | 1 + arch/arm/mach-uniphier/sg-regs.h | 3 +- configs/uniphier_ld20_defconfig | 28 +++++++++ include/configs/uniphier.h | 24 ++++++- 26 files changed, 305 insertions(+), 6 deletions(-) create mode 100644 arch/arm/mach-uniphier/arm64/Makefile create mode 100644 arch/arm/mach-uniphier/arm64/mem_map.c create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c create mode 100644 arch/arm/mach-uniphier/dram/umc-ld20.c create mode 100644 arch/arm/mach-uniphier/early-clk/early-clk-ld20.c create mode 100644 arch/arm/mach-uniphier/init/init-ld20.c create mode 100644 configs/uniphier_ld20_defconfig -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot