| Message ID | 20230121091237.2734272-1-dmitry.baryshkov@linaro.org |
|---|---|
| State | Accepted |
| Commit | 240fb292d3aeb20015d1ab3805fb561be8a9c6f5 |
| Headers | show |
| Series | [v2] ARM: dts: qcom: apq8064: add second DSI host and PHY | expand |
On 21.01.2023 10:12, Dmitry Baryshkov wrote: > Add second DSI host and PHY available on the APQ8064 platform. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad P.S. looking into RPM XO on this platform seems like a good idea too, though I am not sure how it works on pre-SMD SoCs.. > > Changes since v1: > - Switched dsi1 to dsi1 clocks by default > - Indentation and ordering fixes (noted by Konrad) > > --- > arch/arm/boot/dts/qcom-apq8064.dtsi | 78 ++++++++++++++++++++++++++++- > 1 file changed, 76 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi > index b7e5b45e1c04..92aa2b081901 100644 > --- a/arch/arm/boot/dts/qcom-apq8064.dtsi > +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi > @@ -865,8 +865,8 @@ mmcc: clock-controller@4000000 { > <&gcc PLL8_VOTE>, > <&dsi0_phy 1>, > <&dsi0_phy 0>, > - <0>, > - <0>, > + <&dsi1_phy 1>, > + <&dsi1_phy 0>, > <&hdmi_phy>; > clock-names = "pxo", > "pll3", > @@ -1342,6 +1342,80 @@ dsi0_phy: phy@4700200 { > status = "disabled"; > }; > > + dsi1: dsi@5800000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x05800000 0x200>; > + reg-names = "dsi_ctrl"; > + > + clocks = <&mmcc DSI2_M_AHB_CLK>, > + <&mmcc DSI2_S_AHB_CLK>, > + <&mmcc AMP_AHB_CLK>, > + <&mmcc DSI2_CLK>, > + <&mmcc DSI2_BYTE_CLK>, > + <&mmcc DSI2_PIXEL_CLK>, > + <&mmcc DSI2_ESC_CLK>; > + clock-names = "iface", > + "bus", > + "core_mmss", > + "src", > + "byte", > + "pixel", > + "core"; > + > + assigned-clocks = <&mmcc DSI2_BYTE_SRC>, > + <&mmcc DSI2_ESC_SRC>, > + <&mmcc DSI2_SRC>, > + <&mmcc DSI2_PIXEL_SRC>; > + assigned-clock-parents = <&dsi1_phy 0>, > + <&dsi1_phy 0>, > + <&dsi1_phy 1>, > + <&dsi1_phy 1>; > + > + syscon-sfpb = <&mmss_sfpb>; > + phys = <&dsi1_phy>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi1_in: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi1_out: endpoint { > + }; > + }; > + }; > + }; > + > + > + dsi1_phy: dsi-phy@5800200 { > + compatible = "qcom,dsi-phy-28nm-8960"; > + reg = <0x05800200 0x100>, > + <0x05800300 0x200>, > + <0x05800500 0x5c>; > + reg-names = "dsi_pll", > + "dsi_phy", > + "dsi_phy_regulator"; > + clock-names = "iface", > + "ref"; > + clocks = <&mmcc DSI2_M_AHB_CLK>, > + <&pxo_board>; > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > > mdp_port0: iommu@7500000 { > compatible = "qcom,apq8064-iommu";
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index b7e5b45e1c04..92aa2b081901 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -865,8 +865,8 @@ mmcc: clock-controller@4000000 { <&gcc PLL8_VOTE>, <&dsi0_phy 1>, <&dsi0_phy 0>, - <0>, - <0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, <&hdmi_phy>; clock-names = "pxo", "pll3", @@ -1342,6 +1342,80 @@ dsi0_phy: phy@4700200 { status = "disabled"; }; + dsi1: dsi@5800000 { + compatible = "qcom,mdss-dsi-ctrl"; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x05800000 0x200>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc DSI2_M_AHB_CLK>, + <&mmcc DSI2_S_AHB_CLK>, + <&mmcc AMP_AHB_CLK>, + <&mmcc DSI2_CLK>, + <&mmcc DSI2_BYTE_CLK>, + <&mmcc DSI2_PIXEL_CLK>, + <&mmcc DSI2_ESC_CLK>; + clock-names = "iface", + "bus", + "core_mmss", + "src", + "byte", + "pixel", + "core"; + + assigned-clocks = <&mmcc DSI2_BYTE_SRC>, + <&mmcc DSI2_ESC_SRC>, + <&mmcc DSI2_SRC>, + <&mmcc DSI2_PIXEL_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 1>; + + syscon-sfpb = <&mmss_sfpb>; + phys = <&dsi1_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + + dsi1_phy: dsi-phy@5800200 { + compatible = "qcom,dsi-phy-28nm-8960"; + reg = <0x05800200 0x100>, + <0x05800300 0x200>, + <0x05800500 0x5c>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + clock-names = "iface", + "ref"; + clocks = <&mmcc DSI2_M_AHB_CLK>, + <&pxo_board>; + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; mdp_port0: iommu@7500000 { compatible = "qcom,apq8064-iommu";
Add second DSI host and PHY available on the APQ8064 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Changes since v1: - Switched dsi1 to dsi1 clocks by default - Indentation and ordering fixes (noted by Konrad) --- arch/arm/boot/dts/qcom-apq8064.dtsi | 78 ++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 2 deletions(-)