diff mbox series

[v2,05/10] tcg/loongarch64: Update tcg-insn-defs.c.inc

Message ID 20230118011123.392823-6-richard.henderson@linaro.org
State Superseded
Headers show
Series tcg/loongarch64: Reorg goto_tb and cleanups | expand

Commit Message

Richard Henderson Jan. 18, 2023, 1:11 a.m. UTC 
Regenerate with ADDU16I included:

   $ cd loongarch-opcodes/scripts/go
   $ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-insn-defs.c.inc | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)
 mode change 100644 => 100755 tcg/loongarch64/tcg-insn-defs.c.inc

Comments

WANG Xuerui Jan. 22, 2023, 8:20 a.m. UTC | #1 
On 1/18/23 09:11, Richard Henderson wrote:
> Regenerate with ADDU16I included:
>
>     $ cd loongarch-opcodes/scripts/go
>     $ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/loongarch64/tcg-insn-defs.c.inc | 10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
>   mode change 100644 => 100755 tcg/loongarch64/tcg-insn-defs.c.inc
>
> diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn-defs.c.inc
> old mode 100644
> new mode 100755
> index d162571856..b5bb0c5e73
> --- a/tcg/loongarch64/tcg-insn-defs.c.inc
> +++ b/tcg/loongarch64/tcg-insn-defs.c.inc
> @@ -4,7 +4,7 @@
>    *
>    * This file is auto-generated by genqemutcgdefs from
>    * https://github.com/loongson-community/loongarch-opcodes,
> - * from commit 961f0c60f5b63e574d785995600c71ad5413fdc4.
> + * from commit 25ca7effe9d88101c1cf96c4005423643386d81f.
>    * DO NOT EDIT.
>    */
>   
> @@ -74,6 +74,7 @@ typedef enum {
>       OPC_ANDI = 0x03400000,
>       OPC_ORI = 0x03800000,
>       OPC_XORI = 0x03c00000,
> +    OPC_ADDU16I_D = 0x10000000,
>       OPC_LU12I_W = 0x14000000,
>       OPC_CU32I_D = 0x16000000,
>       OPC_PCADDU2I = 0x18000000,
> @@ -710,6 +711,13 @@ tcg_out_opc_xori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12)
>       tcg_out32(s, encode_djuk12_insn(OPC_XORI, d, j, uk12));
>   }
>   
> +/* Emits the `addu16i.d d, j, sk16` instruction.  */
> +static void __attribute__((unused))
> +tcg_out_opc_addu16i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
> +{
> +    tcg_out32(s, encode_djsk16_insn(OPC_ADDU16I_D, d, j, sk16));
> +}
> +
>   /* Emits the `lu12i.w d, sj20` instruction.  */
>   static void __attribute__((unused))
>   tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, int32_t sj20)

Reviewed-by: WANG Xuerui <git@xen0n.name>
Philippe Mathieu-Daudé Jan. 23, 2023, 8:33 a.m. UTC | #2 
On 18/1/23 02:11, Richard Henderson wrote:
> Regenerate with ADDU16I included:
> 
>     $ cd loongarch-opcodes/scripts/go
>     $ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/loongarch64/tcg-insn-defs.c.inc | 10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
>   mode change 100644 => 100755 tcg/loongarch64/tcg-insn-defs.c.inc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn-defs.c.inc
old mode 100644
new mode 100755
index d162571856..b5bb0c5e73
--- a/tcg/loongarch64/tcg-insn-defs.c.inc
+++ b/tcg/loongarch64/tcg-insn-defs.c.inc
@@ -4,7 +4,7 @@ 
  *
  * This file is auto-generated by genqemutcgdefs from
  * https://github.com/loongson-community/loongarch-opcodes,
- * from commit 961f0c60f5b63e574d785995600c71ad5413fdc4.
+ * from commit 25ca7effe9d88101c1cf96c4005423643386d81f.
  * DO NOT EDIT.
  */
 
@@ -74,6 +74,7 @@  typedef enum {
     OPC_ANDI = 0x03400000,
     OPC_ORI = 0x03800000,
     OPC_XORI = 0x03c00000,
+    OPC_ADDU16I_D = 0x10000000,
     OPC_LU12I_W = 0x14000000,
     OPC_CU32I_D = 0x16000000,
     OPC_PCADDU2I = 0x18000000,
@@ -710,6 +711,13 @@  tcg_out_opc_xori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12)
     tcg_out32(s, encode_djuk12_insn(OPC_XORI, d, j, uk12));
 }
 
+/* Emits the `addu16i.d d, j, sk16` instruction.  */
+static void __attribute__((unused))
+tcg_out_opc_addu16i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
+{
+    tcg_out32(s, encode_djsk16_insn(OPC_ADDU16I_D, d, j, sk16));
+}
+
 /* Emits the `lu12i.w d, sj20` instruction.  */
 static void __attribute__((unused))
 tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, int32_t sj20)