| Message ID | 20230117223942.130170-1-marex@denx.de |
|---|---|
| State | Accepted |
| Commit | ab15670727832c0dcf8324dcb01f8bd6fecdbd89 |
| Headers | show |
| Series | arm64: dts: imx8mp: Improve bluetooth UART on DH electronics i.MX8M Plus DHCOM | expand |
On Tue, Jan 17, 2023 at 11:39:42PM +0100, Marek Vasut wrote: > Use PLL1_80M instead of PLL3 to drive UART2 clock divided down to 80 MHz > instead of 64 MHz to obtain suitable block clock for exact 4 Mbdps, which > is the maximum supported baud rate by the muRata 2AE BT UART. > > The difference here is that at 64 MHz UART block clock, the clock with are > divided by 16 (due to oversampling) to 4 MHz and the baud rate generator > then needs to be set to UBIR+1/UBMR+1 = 1/1 to yield 4 Mbdps . In case of > 80 MHz UART block clock divided by 16 to 5 MHz, the baud rate generator > needs to be set to UBIR+1/UBMR+1 = 4/5 to yield 4 Mbdps . > > Both options are valid and yield the same result, except using the PLL1_80M > output requires fewer clock tree changes, since the PLL1 already generates > the 80 MHz usable for UART, which frees the PLL3 for other uses. > > Suggested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> > Signed-off-by: Marek Vasut <marex@denx.de> Applied, thanks!
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 89266b386ac85..75ac4c91a5a40 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -516,14 +516,15 @@ &uart2 { status = "okay"; /* - * PLL3 at 320 MHz supplies UART2 root with 64 MHz clock, - * which with 16x oversampling yields 4 Mbdps baud base, + * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock, + * which with 16x oversampling yields 5 Mbdps baud base, + * which can be well divided by 5/4 to achieve 4 Mbdps, * which is exactly the maximum rate supported by muRata * 2AE bluetooth UART. */ - assigned-clocks = <&clk IMX8MP_SYS_PLL3>, <&clk IMX8MP_CLK_UART2>; - assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL3_OUT>; - assigned-clock-rates = <320000000>, <64000000>; + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + assigned-clock-rates = <80000000>; bluetooth { pinctrl-names = "default";
Use PLL1_80M instead of PLL3 to drive UART2 clock divided down to 80 MHz instead of 64 MHz to obtain suitable block clock for exact 4 Mbdps, which is the maximum supported baud rate by the muRata 2AE BT UART. The difference here is that at 64 MHz UART block clock, the clock with are divided by 16 (due to oversampling) to 4 MHz and the baud rate generator then needs to be set to UBIR+1/UBMR+1 = 1/1 to yield 4 Mbdps . In case of 80 MHz UART block clock divided by 16 to 5 MHz, the baud rate generator needs to be set to UBIR+1/UBMR+1 = 4/5 to yield 4 Mbdps . Both options are valid and yield the same result, except using the PLL1_80M output requires fewer clock tree changes, since the PLL1 already generates the 80 MHz usable for UART, which frees the PLL3 for other uses. Suggested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Fabio Estevam <festevam@gmail.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)