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[2/2] ARM: keystone2: Add missing privilege ID settings

Message ID 1458746059-17893-3-git-send-email-nm@ti.com
State Accepted
Commit 2283284b05326bf1384873f2a59b77fe0d9b2f8f
Headers show

Commit Message

Nishanth Menon March 23, 2016, 3:14 p.m. UTC 
Add missing Privilege ID settings for KS2 SoCs.

Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
  http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
  http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
  http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
  http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)

Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K    | K2L       | K2E       | K2G
-------+-----------+-----------+-----------+---------
0      | C66x 0    | C66x 0    | C66x 0    | C66x 0
1      | C66x 1    | C66x 1    | Reserved  | ARM
2      | C66x 2    | C66x 2    | Reserved  | ICSS0
3      | C66x 3    | C66x 3    | Reserved  | ICSS1
4      | C66x 4    | Reserved  | Reserved  | NETCP
5      | C66x 5    | Reserved  | Reserved  | CPIE
6      | C66x 6    | Reserved  | Reserved  | USB
7      | C66x 7    | Reserved  | Reserved  | Reserved
8      | ARM       | ARM       | ARM       | MLB
9      | NetCP     | NetCP     | NetCP     | PMMC
10     | QM_PDSP   | QM_PDSP   | QM_PDSP   | DSS
11     | PCIe_0    | PCIe_0    | PCIe_0    | MMC
12     | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
13     | Reserved  | Reserved  | PCIe_1    | Reserved
14     | HyperLink | PCIe_1    | HyperLink | Reserved
15     | Reserved  | Reserved  | TSIP      | Reserved
-------+-----------+-----------+-----------+---------

NOTE: Few of these might have default configurations, however,
since most are software configurable, it is better to explicitly
configure the system to have a known default state.

Without programming these, we end up seeing lack of coherency on certain
peripherals resulting in inexplicable failures (such as USB peripheral's
DMA data not appearing on ARM etc and weird workarounds being done by
drivers including cache flushes which tend to have system wide
performance impact).

By marking these segments as shared, we also ensure SoC wide coherency
is enabled.

Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>

---
 arch/arm/mach-keystone/include/mach/hardware.h | 23 ++++++++++++++++++
 arch/arm/mach-keystone/init.c                  | 32 +++++++++++++++++++++++++-
 2 files changed, 54 insertions(+), 1 deletion(-)

-- 
2.8.0.rc3

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diff mbox

Patch

diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index dd9268fbf209..38d019056a29 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -216,22 +216,45 @@  typedef volatile unsigned int   *dv_reg_p;
 #define KS2_MSMC_CTRL_BASE		0x0bc00000
 #define KS2_MSMC_DATA_BASE		0x0c000000
 
+/* KS2 Generic Privilege ID Settings for MSMC2 */
+#define KS2_MSMC_SEGMENT_C6X_0		0
+#define KS2_MSMC_SEGMENT_C6X_1		1
+#define KS2_MSMC_SEGMENT_C6X_2		2
+#define KS2_MSMC_SEGMENT_C6X_3		3
+#define KS2_MSMC_SEGMENT_C6X_4		4
+#define KS2_MSMC_SEGMENT_C6X_5		5
+#define KS2_MSMC_SEGMENT_C6X_6		6
+#define KS2_MSMC_SEGMENT_C6X_7		7
+
+#define KS2_MSMC_SEGMENT_DEBUG		12
+
 /* KS2 HK/L/E MSMC PRIVIDs  for MSMC2 */
 #define K2HKLE_MSMC_SEGMENT_ARM		8
 #define K2HKLE_MSMC_SEGMENT_NETCP	9
 #define K2HKLE_MSMC_SEGMENT_QM_PDSP	10
 #define K2HKLE_MSMC_SEGMENT_PCIE0	11
 
+/* K2HK specific Privilege ID Settings */
+#define K2HKE_MSMC_SEGMENT_HYPERLINK	14
+
 /* K2L specific Privilege ID Settings */
 #define K2L_MSMC_SEGMENT_PCIE1		14
 
 /* K2E specific Privilege ID Settings */
 #define K2E_MSMC_SEGMENT_PCIE1		13
+#define K2E_MSMC_SEGMENT_TSIP		15
 
 /* K2G specific Privilege ID Settings */
 #define K2G_MSMC_SEGMENT_ARM		1
+#define K2G_MSMC_SEGMENT_ICSS0		2
+#define K2G_MSMC_SEGMENT_ICSS1		3
 #define K2G_MSMC_SEGMENT_NSS		4
 #define K2G_MSMC_SEGMENT_PCIE		5
+#define K2G_MSMC_SEGMENT_USB		6
+#define K2G_MSMC_SEGMENT_MLB		8
+#define K2G_MSMC_SEGMENT_PMMC		9
+#define K2G_MSMC_SEGMENT_DSS		10
+#define K2G_MSMC_SEGMENT_MMC		11
 
 /* MSMC segment size shift bits */
 #define KS2_MSMC_SEG_SIZE_SHIFT		12
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index 2368315ff68c..3b6d5efce1a1 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -98,29 +98,57 @@  static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
 
 static void msmc_k2hkle_common_setup(void)
 {
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
 #ifdef KS2_MSMC_SEGMENT_QM_PDSP
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
 #endif
 	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
+}
+
+static void msmc_k2hk_setup(void)
+{
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
+	msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
 }
 
 static inline void msmc_k2l_setup(void)
 {
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
 	msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
 }
 
 static inline void msmc_k2e_setup(void)
 {
 	msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
+	msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
+	msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
 }
 
-static inline void msmc_k2g_setup(void)
+static void msmc_k2g_setup(void)
 {
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 	msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
 	msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
 	msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
+	msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
+	msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
 }
 
 int arch_cpu_init(void)
@@ -136,6 +164,8 @@  int arch_cpu_init(void)
 			msmc_k2e_setup();
 		else if (cpu_is_k2l())
 			msmc_k2l_setup();
+		else
+			msmc_k2hk_setup();
 	}
 
 	/* Initialize the PCIe-0 to work as Root Complex */