@@ -34,9 +34,6 @@
#define KS2_LPSC_PCIE_1 27
#define KS2_LPSC_XGE 50
-/* MSMC */
-#define KS2_MSMC_SEGMENT_PCIE1 13
-
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
@@ -53,9 +53,6 @@
#define KS2_LPSC_FFTC_B 49
#define KS2_LPSC_IQN_AIL 50
-/* MSMC */
-#define KS2_MSMC_SEGMENT_PCIE1 14
-
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
@@ -215,16 +215,23 @@ typedef volatile unsigned int *dv_reg_p;
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc00000
#define KS2_MSMC_DATA_BASE 0x0c000000
-#ifndef CONFIG_SOC_K2G
-#define KS2_MSMC_SEGMENT_TETRIS 8
-#define KS2_MSMC_SEGMENT_NETCP 9
-#define KS2_MSMC_SEGMENT_QM_PDSP 10
-#define KS2_MSMC_SEGMENT_PCIE0 11
-#else
-#define KS2_MSMC_SEGMENT_TETRIS 1
-#define KS2_MSMC_SEGMENT_NETCP 4
-#define KS2_MSMC_SEGMENT_PCIE0 5
-#endif
+
+/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */
+#define K2HKLE_MSMC_SEGMENT_ARM 8
+#define K2HKLE_MSMC_SEGMENT_NETCP 9
+#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10
+#define K2HKLE_MSMC_SEGMENT_PCIE0 11
+
+/* K2L specific Privilege ID Settings */
+#define K2L_MSMC_SEGMENT_PCIE1 14
+
+/* K2E specific Privilege ID Settings */
+#define K2E_MSMC_SEGMENT_PCIE1 13
+
+/* K2G specific Privilege ID Settings */
+#define K2G_MSMC_SEGMENT_ARM 1
+#define K2G_MSMC_SEGMENT_NSS 4
+#define K2G_MSMC_SEGMENT_PCIE 5
/* MSMC segment size shift bits */
#define KS2_MSMC_SEG_SIZE_SHIFT 12
@@ -96,22 +96,51 @@ static void config_pcie_mode(int pcie_port, enum pci_mode mode)
__raw_writel(val, KS2_DEVCFG);
}
+static void msmc_k2hkle_common_setup(void)
+{
+ msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
+ msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
+#ifdef KS2_MSMC_SEGMENT_QM_PDSP
+ msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
+#endif
+ msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
+}
+
+static inline void msmc_k2l_setup(void)
+{
+ msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
+}
+
+static inline void msmc_k2e_setup(void)
+{
+ msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
+}
+
+static inline void msmc_k2g_setup(void)
+{
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
+ msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
+}
+
int arch_cpu_init(void)
{
chip_configuration_unlock();
icache_enable();
- msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
- msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
-#ifdef KS2_MSMC_SEGMENT_QM_PDSP
- msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
-#endif
- msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+ if (cpu_is_k2g()) {
+ msmc_k2g_setup();
+ } else {
+ msmc_k2hkle_common_setup();
+ if (cpu_is_k2e())
+ msmc_k2e_setup();
+ else if (cpu_is_k2l())
+ msmc_k2l_setup();
+ }
/* Initialize the PCIe-0 to work as Root Complex */
config_pcie_mode(0, ROOTCOMPLEX);
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
- msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
/* Initialize the PCIe-1 to work as Root Complex */
config_pcie_mode(1, ROOTCOMPLEX);
#endif
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC. As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact. Signed-off-by: Nishanth Menon <nm@ti.com> --- arch/arm/mach-keystone/include/mach/hardware-k2e.h | 3 -- arch/arm/mach-keystone/include/mach/hardware-k2l.h | 3 -- arch/arm/mach-keystone/include/mach/hardware.h | 27 +++++++++----- arch/arm/mach-keystone/init.c | 43 ++++++++++++++++++---- 4 files changed, 53 insertions(+), 23 deletions(-) -- 2.8.0.rc3 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot