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[v3,02/14] clk: qcom: clk-alpha-pll: program PLL_TEST/PLL_TEST_U if required

Message ID 20230113120544.59320-3-dmitry.baryshkov@linaro.org
State Accepted
Commit d234c4bcad3978b1b5473a8ae6d4f013a1335a75
Headers show
Series clk: qcom: cpu-8996: stability fixes | expand

Commit Message

Dmitry Baryshkov Jan. 13, 2023, 12:05 p.m. UTC 
Program PLL_TEST and PLL_TEST_U registers if required by the pll
configuration.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Konrad Dybcio Jan. 13, 2023, 2:11 p.m. UTC | #1 
On 13.01.2023 13:05, Dmitry Baryshkov wrote:
> Program PLL_TEST and PLL_TEST_U registers if required by the pll
> configuration.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/clk/qcom/clk-alpha-pll.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index f9e4cfd7261c..e266379427f2 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -358,6 +358,11 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>  
>  	regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
>  
> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
> +						config->test_ctl_val);
> +	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
> +						config->test_ctl_hi_val);
> +
>  	if (pll->flags & SUPPORTS_FSM_MODE)
>  		qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
>  }
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index f9e4cfd7261c..e266379427f2 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -358,6 +358,11 @@  void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 
 	regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
 
+	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
+						config->test_ctl_val);
+	clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
+						config->test_ctl_hi_val);
+
 	if (pll->flags & SUPPORTS_FSM_MODE)
 		qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
 }