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[1/2] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x

Message ID 20230110225547.1563119-2-jonas@kwiboo.se
State Accepted
Commit 64b69474edf3b885c19a89bb165f978ba1b4be00
Headers show
Series [1/2] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x | expand

Commit Message

Jonas Karlman Jan. 10, 2023, 10:55 p.m. UTC
clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
and not to 32 kHz on RK356x.

Fix this by assigning clk_rtc_32k a rate of 32768, also assign the parent
to clk_rtc32k_frac.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 5706c3e24f0a..e319699f5e39 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -422,8 +422,9 @@  cru: clock-controller@fdd20000 {
 		clock-names = "xin24m";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
-		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
-		assigned-clock-rates = <1200000000>, <200000000>;
+		assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
+		assigned-clock-rates = <32768>, <1200000000>, <200000000>;
+		assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
 		rockchip,grf = <&grf>;
 	};