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[v2,6/6] riscv: dts: allwinner: d1: Add the IOMMU node

Message ID 20230103010903.11181-7-samuel@sholland.org
State New
Headers show
Series None | expand

Commit Message

Samuel Holland Jan. 3, 2023, 1:09 a.m. UTC
D1 contains an IOMMU for its video-related hardware. Add the node, and
hook it up to the masters which are already described in the devicetree.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

Changes in v2:
 - New patch for v2

 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Jernej Škrabec Jan. 4, 2023, 10:07 p.m. UTC | #1
Dne torek, 03. januar 2023 ob 02:09:03 CET je Samuel Holland napisal(a):
> D1 contains an IOMMU for its video-related hardware. Add the node, and
> hook it up to the masters which are already described in the devicetree.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej
Samuel Holland Jan. 14, 2023, 5:17 p.m. UTC | #2
Hi Joerg,

On 1/13/23 09:35, Joerg Roedel wrote:
> On Mon, Jan 02, 2023 at 07:09:03PM -0600, Samuel Holland wrote:
>>  arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 10 ++++++++++
> 
> This file does not exist in v6.2-rc3, what tree ist this patch-set based
> on?

The D1/D1s/T113 devicetree is added by this series[1], which will be
merged through the sunxi -> soc tree. That patch is included to show how
the new compatible string is used, and that the driver changes have been
tested. You can ignore it when merging the binding/driver changes. The
rest of the series should apply cleanly to v6.2-rc3.

Regards,
Samuel

[1]:
https://lore.kernel.org/linux-sunxi/20221231233851.24923-1-samuel@sholland.org/
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index dff363a3c934..ade50f1e01a4 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -138,6 +138,14 @@  ccu: clock-controller@2001000 {
 			#reset-cells = <1>;
 		};
 
+		iommu: iommu@2010000 {
+			compatible = "allwinner,sun20i-d1-iommu";
+			reg = <0x2010000 0x10000>;
+			interrupts = <SOC_PERIPHERAL_IRQ(64) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_IOMMU>;
+			#iommu-cells = <1>;
+		};
+
 		dmic: dmic@2031000 {
 			compatible = "allwinner,sun20i-d1-dmic",
 				     "allwinner,sun50i-h6-dmic";
@@ -574,6 +582,7 @@  mixer0: mixer@5100000 {
 				 <&display_clocks CLK_MIXER0>;
 			clock-names = "bus", "mod";
 			resets = <&display_clocks RST_MIXER0>;
+			iommus = <&iommu 2>;
 
 			ports {
 				#address-cells = <1>;
@@ -596,6 +605,7 @@  mixer1: mixer@5200000 {
 				 <&display_clocks CLK_MIXER1>;
 			clock-names = "bus", "mod";
 			resets = <&display_clocks RST_MIXER1>;
+			iommus = <&iommu 2>;
 
 			ports {
 				#address-cells = <1>;