| Message ID | 20221215190404.398788-2-they@mint.lgbt |
|---|---|
| State | Superseded |
| Headers | show |
| Series | None | expand |
On 16/12/2022 08:24, Konrad Dybcio wrote: > > On 15.12.2022 20:04, Lux Aliaga wrote: >> Adds a UFS host controller node and its corresponding PHY to >> the sm6125 platform. >> >> Signed-off-by: Lux Aliaga <they@mint.lgbt> >> --- > Please include a changelog, I don't know what you changed and > what you didn't. Also, you sent 4 revisions in one day, not > letting others review it. > > >> arch/arm64/boot/dts/qcom/sm6125.dtsi | 67 ++++++++++++++++++++++++++++ >> 1 file changed, 67 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi >> index 7e25a4f85594..b64c5bc1452f 100644 >> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >> @@ -508,6 +508,73 @@ sdhc_2: mmc@4784000 { >> status = "disabled"; >> }; >> >> + ufs_mem_hc: ufs@4804000 { >> + compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; >> + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; >> + reg-names = "std", "ice"; >> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >> + phys = <&ufs_mem_phy_lanes>; >> + phy-names = "ufsphy"; >> + lanes-per-direction = <1>; >> + #reset-cells = <1>; >> + resets = <&gcc GCC_UFS_PHY_BCR>; >> + reset-names = "rst"; >> + >> + clock-names = "core_clk", >> + "bus_aggr_clk", >> + "iface_clk", >> + "core_clk_unipro", >> + "ref_clk", >> + "tx_lane0_sync_clk", >> + "rx_lane0_sync_clk", >> + "ice_core_clk"; >> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_UFS_PHY_AHB_CLK>, >> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >> + <&rpmcc RPM_SMD_XO_CLK_SRC>, >> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; >> + freq-table-hz = <50000000 240000000>, >> + <0 0>, >> + <0 0>, >> + <37500000 150000000>, >> + <0 0>, >> + <0 0>, >> + <0 0>, >> + <75000000 300000000>; >> + >> + non-removable; >> + status = "disabled"; >> + }; >> + >> + ufs_mem_phy: phy@4807000 { >> + compatible = "qcom,sm6115-qmp-ufs-phy"; > Krzysztof asked you to add a SoC-specific compatible in v1. I'm working on adding a new compatible for sm6125's UFS PHY. Should I copy sm6115's tables or just reference them in the sm6125's config in drivers/phy/qualcomm/phy-qcom-qmp-ufs.c?
On 20/12/2022 22:30, Dmitry Baryshkov wrote: > On Tue, 20 Dec 2022 at 21:33, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: >> >> >> >> On 20.12.2022 19:57, Lux Aliaga wrote: >>> On 16/12/2022 08:24, Konrad Dybcio wrote: >>> >>>> >>>> On 15.12.2022 20:04, Lux Aliaga wrote: >>>>> Adds a UFS host controller node and its corresponding PHY to >>>>> the sm6125 platform. >>>>> >>>>> Signed-off-by: Lux Aliaga <they@mint.lgbt> >>>>> --- >>>> Please include a changelog, I don't know what you changed and >>>> what you didn't. Also, you sent 4 revisions in one day, not >>>> letting others review it. >>>> >>>> >>>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 67 ++++++++++++++++++++++++++++ >>>>> 1 file changed, 67 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>>> index 7e25a4f85594..b64c5bc1452f 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi >>>>> @@ -508,6 +508,73 @@ sdhc_2: mmc@4784000 { >>>>> status = "disabled"; >>>>> }; >>>>> + ufs_mem_hc: ufs@4804000 { >>>>> + compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; >>>>> + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; >>>>> + reg-names = "std", "ice"; >>>>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >>>>> + phys = <&ufs_mem_phy_lanes>; >>>>> + phy-names = "ufsphy"; >>>>> + lanes-per-direction = <1>; >>>>> + #reset-cells = <1>; >>>>> + resets = <&gcc GCC_UFS_PHY_BCR>; >>>>> + reset-names = "rst"; >>>>> + >>>>> + clock-names = "core_clk", >>>>> + "bus_aggr_clk", >>>>> + "iface_clk", >>>>> + "core_clk_unipro", >>>>> + "ref_clk", >>>>> + "tx_lane0_sync_clk", >>>>> + "rx_lane0_sync_clk", >>>>> + "ice_core_clk"; >>>>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, >>>>> + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, >>>>> + <&gcc GCC_UFS_PHY_AHB_CLK>, >>>>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >>>>> + <&rpmcc RPM_SMD_XO_CLK_SRC>, >>>>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >>>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, >>>>> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; >>>>> + freq-table-hz = <50000000 240000000>, >>>>> + <0 0>, >>>>> + <0 0>, >>>>> + <37500000 150000000>, >>>>> + <0 0>, >>>>> + <0 0>, >>>>> + <0 0>, >>>>> + <75000000 300000000>; >>>>> + >>>>> + non-removable; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + ufs_mem_phy: phy@4807000 { >>>>> + compatible = "qcom,sm6115-qmp-ufs-phy"; >>>> Krzysztof asked you to add a SoC-specific compatible in v1. >>> I'm working on adding a new compatible for sm6125's UFS PHY. Should I copy sm6115's tables or just reference them in the sm6125's config in drivers/phy/qualcomm/phy-qcom-qmp-ufs.c? >> If they're identical, you can just do something like this: >> >> compatible = "qcom,sm6125-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; > > Ugh. I'd prefer to see either of the compatible strings here, but not > both of them. I hit send too quick, so the justification didn't get in. Currently we list a single compatibility string for all QMP PHYs. Having just a single exception stands out, so I'd advise against doing that (despite Konrad's suggestion being technically correct). > >> >> And ensure your newly added compatible is documented in bindings. >> This way, the driver will fall back to the 6115 compatible that's >> defined in .c, but if we ever need to adjust something specific >> for 6125, we will just use the define that we added here. That's >> important, as we're supposed to stay backwards-compatible with >> old device trees. >> >> Also, wrap your emails at around 80 chars or so, some people >> are grumpy about that :P >> >> Konrad >>> > > >
On Wed, Dec 21, 2022 at 12:34:46AM -0300, Lux Aliaga wrote: > > On 16/12/2022 08:24, Konrad Dybcio wrote: > > > > On 15.12.2022 20:04, Lux Aliaga wrote: > >> Adds a UFS host controller node and its corresponding PHY to > >> the sm6125 platform. > >> + reg = <0x04807000 0x1c4>; > >> + > >> + power-domains = <&gcc UFS_PHY_GDSC>; > >> + > >> + clock-names = "ref", "ref_aux"; > >> + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > >> + > >> + resets = <&ufs_mem_hc 0>; > >> + reset-names = "ufsphy"; > >> + > >> + #address-cells = <1>; > >> + #size-cells = <1>; > >> + ranges; > >> + > >> + status = "disabled"; > >> + > >> + ufs_mem_phy_lanes: lanes@4807400 { > >> + reg = <0x4807400 0x098>, > >> + <0x4807600 0x130>, > >> + <0x4807c00 0x16c>; > >> + #phy-cells = <0>; > >> + }; > > I believe this is deprecated. See [1]. > > [1] https://lore.kernel.org/linux-arm-msm/20221104092045.17410-1-johan+linaro@kernel.org/T/#m988f3fe3d83b76bac247aea2d9dac34f37728d65 > I've looked into the documentation and this is only for the sc8280xp. > This PHY is defined as it is for the msm8996 and derivatives. No, it's not just for sc8280xp. It's intended for all new bindings (i.e. do not add more platforms to the msm8996 schema file). Johan
On 21/12/2022 04:12, Johan Hovold wrote: > On Wed, Dec 21, 2022 at 12:34:46AM -0300, Lux Aliaga wrote: >> On 16/12/2022 08:24, Konrad Dybcio wrote: >>> On 15.12.2022 20:04, Lux Aliaga wrote: >>>> Adds a UFS host controller node and its corresponding PHY to >>>> the sm6125 platform. >>>> + reg = <0x04807000 0x1c4>; >>>> + >>>> + power-domains = <&gcc UFS_PHY_GDSC>; >>>> + >>>> + clock-names = "ref", "ref_aux"; >>>> + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; >>>> + >>>> + resets = <&ufs_mem_hc 0>; >>>> + reset-names = "ufsphy"; >>>> + >>>> + #address-cells = <1>; >>>> + #size-cells = <1>; >>>> + ranges; >>>> + >>>> + status = "disabled"; >>>> + >>>> + ufs_mem_phy_lanes: lanes@4807400 { >>>> + reg = <0x4807400 0x098>, >>>> + <0x4807600 0x130>, >>>> + <0x4807c00 0x16c>; >>>> + #phy-cells = <0>; >>>> + }; >>> I believe this is deprecated. See [1]. >>> [1] https://lore.kernel.org/linux-arm-msm/20221104092045.17410-1-johan+linaro@kernel.org/T/#m988f3fe3d83b76bac247aea2d9dac34f37728d65 >> I've looked into the documentation and this is only for the sc8280xp. >> This PHY is defined as it is for the msm8996 and derivatives. > No, it's not just for sc8280xp. It's intended for all new bindings (i.e. > do not add more platforms to the msm8996 schema file). > > Johan Alright. But this would mean writing a new config for the sm6125 specifically. If we're changing how the bindings for UFS PHYs work, wouldn't it make more sense to change the sm6115 config instead, since they're defined pretty much the same?
On Thu, Dec 22, 2022 at 12:57:09AM -0300, Lux Aliaga wrote: > On 21/12/2022 04:12, Johan Hovold wrote: > > > On Wed, Dec 21, 2022 at 12:34:46AM -0300, Lux Aliaga wrote: > >> On 16/12/2022 08:24, Konrad Dybcio wrote: > >>> On 15.12.2022 20:04, Lux Aliaga wrote: > >>>> Adds a UFS host controller node and its corresponding PHY to > >>>> the sm6125 platform. > >>>> + reg = <0x04807000 0x1c4>; > >>>> + > >>>> + power-domains = <&gcc UFS_PHY_GDSC>; > >>>> + > >>>> + clock-names = "ref", "ref_aux"; > >>>> + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > >>>> + > >>>> + resets = <&ufs_mem_hc 0>; > >>>> + reset-names = "ufsphy"; > >>>> + > >>>> + #address-cells = <1>; > >>>> + #size-cells = <1>; > >>>> + ranges; > >>>> + > >>>> + status = "disabled"; > >>>> + > >>>> + ufs_mem_phy_lanes: lanes@4807400 { > >>>> + reg = <0x4807400 0x098>, > >>>> + <0x4807600 0x130>, > >>>> + <0x4807c00 0x16c>; > >>>> + #phy-cells = <0>; > >>>> + }; > >>> I believe this is deprecated. See [1]. > >>> [1] https://lore.kernel.org/linux-arm-msm/20221104092045.17410-1-johan+linaro@kernel.org/T/#m988f3fe3d83b76bac247aea2d9dac34f37728d65 > >> I've looked into the documentation and this is only for the sc8280xp. > >> This PHY is defined as it is for the msm8996 and derivatives. > > No, it's not just for sc8280xp. It's intended for all new bindings (i.e. > > do not add more platforms to the msm8996 schema file). > Alright. But this would mean writing a new config for the sm6125 > specifically. If we're changing how the bindings for UFS PHYs work, > wouldn't it make more sense to change the sm6115 config instead, since > they're defined pretty much the same? It can be done that way too, that is, you can add the missing offsets to the sm6115 config and use it for both sm6115 and sm6125 if they are really that closely related. The driver will only parse the old-style bindings (for sm6115) if the PHY node has a child. You still need to add a new compatible for sm6125 to the PHY driver, though, which appears to be missing in this series. Johan
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 7e25a4f85594..b64c5bc1452f 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -508,6 +508,73 @@ sdhc_2: mmc@4784000 { status = "disabled"; }; + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg-names = "std", "ice"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + freq-table-hz = <50000000 240000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <75000000 300000000>; + + non-removable; + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6115-qmp-ufs-phy"; + reg = <0x04807000 0x1c4>; + + power-domains = <&gcc UFS_PHY_GDSC>; + + clock-names = "ref", "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + ufs_mem_phy_lanes: lanes@4807400 { + reg = <0x4807400 0x098>, + <0x4807600 0x130>, + <0x4807c00 0x16c>; + #phy-cells = <0>; + }; + }; + usb3: usb@4ef8800 { compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; reg = <0x04ef8800 0x400>;
Adds a UFS host controller node and its corresponding PHY to the sm6125 platform. Signed-off-by: Lux Aliaga <they@mint.lgbt> --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 67 ++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+)