| Message ID | 20221212180732.79167-3-sudip.mukherjee@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for enhanced SPI for Designware SPI controllers | expand |
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 77c23772bb3d9..8c47a4d14b666 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -346,7 +346,9 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, dw_writel(dws, DW_SPI_CTRLR0, cr0); if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD || - cfg->tmode == DW_SPI_CTRLR0_TMOD_RO) + cfg->tmode == DW_SPI_CTRLR0_TMOD_RO || + (cfg->tmode == DW_SPI_CTRLR0_TMOD_TO && + cfg->spi_frf != DW_SPI_CTRLR0_SPI_FRF_STD_SPI)) dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); /* Note DW APB SSI clock divider doesn't support odd numbers */
If the transfer of Transmit only mode is using dual/quad/octal SPI then NDF needs to be updated with the number of data frames. If the Transmit FIFO goes empty in-between, DWC_ssi masks the serial clock and wait for rest of the data until the programmed amount of frames are transferred successfully. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com> --- drivers/spi/spi-dw-core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)