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[1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells

Message ID 20221213160112.1900410-1-l.stach@pengutronix.de
State Accepted
Commit ba70e1733238b3d4b53a5f030db629d3331110ec
Headers show
Series [1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells | expand

Commit Message

Lucas Stach Dec. 13, 2022, 4:01 p.m. UTC 
The HSIO blk-ctrl has a internal PLL, which can be used as a reference
clock for the PCIe PHY. Add clock-cells to the binding to allow the
driver to expose this PLL.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
index c29181a9745b..1cc7c2bdf2bb 100644
--- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml
@@ -39,6 +39,9 @@  properties:
       - const: pcie
       - const: pcie-phy
 
+  '#clock-cells':
+    const: 1
+
   clocks:
     minItems: 2
     maxItems: 2
@@ -85,4 +88,5 @@  examples:
         power-domain-names = "bus", "usb", "usb-phy1",
                              "usb-phy2", "pcie", "pcie-phy";
         #power-domain-cells = <1>;
+        #clock-cells = <0>;
     };