| Message ID | 20221213140409.772-2-quic_sibis@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for CPUCP mailbox controller | expand |
Additional patches got tagged along. Please ignore. On 12/13/22 19:34, Sibi Sankar wrote: > Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox > controller. > > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- > .../bindings/mailbox/qcom,cpucp-mbox.yaml | 51 ++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml > new file mode 100644 > index 000000000000..1f7e1204cda0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller > + > +maintainers: > + - Sibi Sankar <quic_sibis@qti.qualcomm.com> > + > +description: > + The CPUSS Control Processor (CPUCP) mailbox controller enables communication > + between AP and CPUCP by acting as a doorbell between them. > + > +properties: > + compatible: > + items: > + - enum: > + - qcom,sc7280-cpucp-mbox > + - const: qcom,cpucp-mbox > + > + reg: > + items: > + - description: CPUCP tx register region > + - description: CPUCP rx register region > + > + interrupts: > + maxItems: 1 > + > + "#mbox-cells": > + const: 0 > + > +required: > + - compatible > + - reg > + - interrupts > + - "#mbox-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + mailbox@17400000 { > + compatible = "qcom,sc7280-cpucp-mbox", "qcom,cpucp-mbox"; > + reg = <0x0 0x17c00000 0x0 0x10>, <0x0 0x18590300 0x0 0x700>; > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <0>; > + };
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml new file mode 100644 index 000000000000..1f7e1204cda0 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller + +maintainers: + - Sibi Sankar <quic_sibis@qti.qualcomm.com> + +description: + The CPUSS Control Processor (CPUCP) mailbox controller enables communication + between AP and CPUCP by acting as a doorbell between them. + +properties: + compatible: + items: + - enum: + - qcom,sc7280-cpucp-mbox + - const: qcom,cpucp-mbox + + reg: + items: + - description: CPUCP tx register region + - description: CPUCP rx register region + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mailbox@17400000 { + compatible = "qcom,sc7280-cpucp-mbox", "qcom,cpucp-mbox"; + reg = <0x0 0x17c00000 0x0 0x10>, <0x0 0x18590300 0x0 0x700>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <0>; + };
Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox controller. Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- .../bindings/mailbox/qcom,cpucp-mbox.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml