diff mbox series

[v7,06/17] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando Elba System Resource chip

Message ID 20221116010453.41320-1-blarson@amd.com
State New
Headers show
Series None | expand

Commit Message

Brad Larson Nov. 16, 2022, 1:04 a.m. UTC 
Add support for the AMD Pensando Elba SoC System Resource chip
using the SPI interface.

Signed-off-by: Brad Larson <blarson@amd.com>
---

v7:
 - Use system-controller for the device with four chip-selects
   connected over spi.
 - Delete child by moving reset-controller into the parent.
 - Updated and used dtschema-2022.11 and yamllint-1.28.0

v6:
 - Expand description, rename nodes and change compatible usage

v5:
 - Change to AMD Pensando instead of Pensando

v4:
 - Change Maintained to Supported

 .../bindings/mfd/amd,pensando-elbasr.yaml     | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml

Comments

Krzysztof Kozlowski Nov. 16, 2022, 8:46 a.m. UTC | #1 
On 16/11/2022 02:04, Brad Larson wrote:
> Add support for the AMD Pensando Elba SoC System Resource chip
> using the SPI interface.
> 

This is patch 6/17, but it misses in-reply-to headers. Where is the
rest? Lore also doesn't know...
https://lore.kernel.org/all/20221116010453.41320-1-blarson@amd.com/

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml
new file mode 100644
index 000000000000..ac44d7d0a91a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml
@@ -0,0 +1,74 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/amd,pensando-elbasr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD Pensando Elba SoC Resource Controller bindings
+
+description: |
+  AMD Pensando Elba SoC Resource Controller functions are
+  accessed with four chip-selects.  Reset control is on CS0.
+
+maintainers:
+  - Brad Larson <blarson@amd.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - amd,pensando-elbasr
+
+  "#reset-cells":
+    const: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - spi-max-frequency
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        num-cs = <4>;
+        status = "okay";
+
+        rstc: system-controller@0 {
+            compatible = "amd,pensando-elbasr";
+            reg = <0>;
+            spi-max-frequency = <12000000>;
+            #reset-cells = <1>;
+        };
+
+        system-controller@1 {
+            compatible = "amd,pensando-elbasr";
+            reg = <1>;
+            spi-max-frequency = <12000000>;
+        };
+
+        system-controller@2 {
+            compatible = "amd,pensando-elbasr";
+            reg = <2>;
+            spi-max-frequency = <12000000>;
+            interrupt-parent = <&porta>;
+            interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+        };
+
+        system-controller@3 {
+            compatible = "amd,pensando-elbasr";
+            reg = <3>;
+            spi-max-frequency = <12000000>;
+        };
+    };