| Message ID | 20221116115046.2687244-1-abel.vesa@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM8550 compatible | expand |
On 16/11/2022 12:50, Abel Vesa wrote: > Add compatible for EPSS CPUFREQ-HW on SM8550. > Also document the interrupts. None of other variants had interrupts so far, so you are adding it for new SoC, right? Or documenting existing usage? If the first, you need allOf:if:then. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e58c55f78aaa..83d814afc780 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -27,6 +27,7 @@ properties: - enum: - qcom,sm6375-cpufreq-epss - qcom,sm8250-cpufreq-epss + - qcom,sm8550-cpufreq-epss - const: qcom,cpufreq-epss reg: @@ -53,6 +54,12 @@ properties: - const: xo - const: alternate + interrupts: + maxItems: 3 + + interrupt-names: + maxItems: 3 + '#freq-domain-cells': const: 1
Add compatible for EPSS CPUFREQ-HW on SM8550. Also document the interrupts. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 7 +++++++ 1 file changed, 7 insertions(+)