| Message ID | 20221110160931.101539-1-biju.das.jz@bp.renesas.com |
|---|---|
| State | Accepted |
| Commit | c6b1737f45ca708fee76a30afb4a7b0247455749 |
| Headers | show |
| Series | arm64: dts: renesas: r9a09g011: Add L2 Cache node | expand |
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index ebaa8cdd747d..7b949e40745a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -37,8 +37,15 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; reg = <0>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; }; + + L2_CA53: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; }; soc: soc {
The Cortex-A53 processor on RZ/V2M has 512 KB L2 Cache. Add L2 Cache node to SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)