| Message ID | 1667792089-4904-1-git-send-email-TonyWWang-oc@zhaoxin.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] x86/acpi/cstate: Optimize ARB_DISABLE on Centaur CPUs | expand |
On Mon, Nov 7, 2022 at 4:35 AM Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> wrote: > > On all recent Centaur platforms, ARB_DISABLE is handled by PMU > automatically while entering C3 type state. No need for OS to > issue the ARB_DISABLE, so set bm_control to zero to indicate that. > > Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Or x86 maintainers please let me know if you want me to take care of this. Thanks! > --- > Changes in V2: > - fix typo in comments. > --- > arch/x86/kernel/acpi/cstate.c | 26 +++++++++++++++++--------- > 1 file changed, 17 insertions(+), 9 deletions(-) > > diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c > index 7945eae..da71679 100644 > --- a/arch/x86/kernel/acpi/cstate.c > +++ b/arch/x86/kernel/acpi/cstate.c > @@ -52,17 +52,25 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, > if (c->x86_vendor == X86_VENDOR_INTEL && > (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f))) > flags->bm_control = 0; > - /* > - * For all recent Centaur CPUs, the ucode will make sure that each > - * core can keep cache coherence with each other while entering C3 > - * type state. So, set bm_check to 1 to indicate that the kernel > - * doesn't need to execute a cache flush operation (WBINVD) when > - * entering C3 type state. > - */ > + > if (c->x86_vendor == X86_VENDOR_CENTAUR) { > if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f && > - c->x86_stepping >= 0x0e)) > - flags->bm_check = 1; > + c->x86_stepping >= 0x0e)) { > + /* > + * For all recent Centaur CPUs, the ucode will make sure that each > + * core can keep cache coherence with each other while entering C3 > + * type state. So, set bm_check to 1 to indicate that the kernel > + * doesn't need to execute a cache flush operation (WBINVD) when > + * entering C3 type state. > + */ > + flags->bm_check = 1; > + /* > + * For all recent Centaur platforms, ARB_DISABLE is a nop. > + * Set bm_control to zero to indicate that ARB_DISABLE is > + * not required while entering C3 type state. > + */ > + flags->bm_control = 0; > + } > } > > if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { > -- > 2.7.4 >
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index 7945eae..da71679 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -52,17 +52,25 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, if (c->x86_vendor == X86_VENDOR_INTEL && (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f))) flags->bm_control = 0; - /* - * For all recent Centaur CPUs, the ucode will make sure that each - * core can keep cache coherence with each other while entering C3 - * type state. So, set bm_check to 1 to indicate that the kernel - * doesn't need to execute a cache flush operation (WBINVD) when - * entering C3 type state. - */ + if (c->x86_vendor == X86_VENDOR_CENTAUR) { if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f && - c->x86_stepping >= 0x0e)) - flags->bm_check = 1; + c->x86_stepping >= 0x0e)) { + /* + * For all recent Centaur CPUs, the ucode will make sure that each + * core can keep cache coherence with each other while entering C3 + * type state. So, set bm_check to 1 to indicate that the kernel + * doesn't need to execute a cache flush operation (WBINVD) when + * entering C3 type state. + */ + flags->bm_check = 1; + /* + * For all recent Centaur platforms, ARB_DISABLE is a nop. + * Set bm_control to zero to indicate that ARB_DISABLE is + * not required while entering C3 type state. + */ + flags->bm_control = 0; + } } if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
On all recent Centaur platforms, ARB_DISABLE is handled by PMU automatically while entering C3 type state. No need for OS to issue the ARB_DISABLE, so set bm_control to zero to indicate that. Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> --- Changes in V2: - fix typo in comments. --- arch/x86/kernel/acpi/cstate.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-)