| Message ID | 20221106085034.12582-3-linux@fw-web.de |
|---|---|
| State | New |
| Headers | show |
| Series | Add BananaPi R3 | expand |
On 06/11/2022 09:50, Frank Wunderlich wrote: > From: Sam Shih <sam.shih@mediatek.com> > > This patch adds spi support for MT7986. > > Signed-off-by: Sam Shih <sam.shih@mediatek.com> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > --- > arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++ > arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++ > arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++ > 3 files changed, 98 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts > index 6189436fe31d..58f7e6b169bf 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts > +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts > @@ -55,6 +55,20 @@ switch: switch@0 { > }; > > &pio { > + spi_flash_pins: spi-flash-pins { > + mux { > + function = "spi"; > + groups = "spi0", "spi0_wp_hold"; > + }; > + }; > + > + spic_pins: spic-pins { > + mux { > + function = "spi"; > + groups = "spi1_2"; > + }; > + }; > + > uart1_pins: uart1-pins { > mux { > function = "uart"; > @@ -101,6 +115,27 @@ conf { > }; > }; > > +&spi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&spi_flash_pins>; > + cs-gpios = <0>, <0>; > + status = "okay"; > + spi_nand: spi_nand@0 { > + compatible = "spi-nand"; > + reg = <0>; > + spi-max-frequency = <10000000>; > + spi-tx-buswidth = <4>; > + spi-rx-buswidth = <4>; > + }; > +}; > + > +&spi1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&spic_pins>; > + cs-gpios = <0>, <0>; > + status = "okay"; > +}; > + > &switch { > ports { > #address-cells = <1>; > diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > index 226648f48df2..6d881095d933 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > @@ -112,6 +112,34 @@ infracfg: infracfg@10001000 { > #clock-cells = <1>; > }; > > + spi0: spi@1100a000 { > + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0 0x1100a000 0 0x100>; > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&topckgen CLK_TOP_MPLL_D2>, > + <&topckgen CLK_TOP_SPI_SEL>, > + <&infracfg CLK_INFRA_SPI0_CK>, > + <&infracfg CLK_INFRA_SPI0_HCK_CK>; > + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; > + status = "disabled"; > + }; > + > + spi1: spi@1100b000 { > + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0 0x1100b000 0 0x100>; > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&topckgen CLK_TOP_MPLL_D2>, > + <&topckgen CLK_TOP_SPIM_MST_SEL>, > + <&infracfg CLK_INFRA_SPI1_CK>, > + <&infracfg CLK_INFRA_SPI1_HCK_CK>; > + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; > + status = "disabled"; > + }; > + > topckgen: topckgen@1001b000 { > compatible = "mediatek,mt7986-topckgen", "syscon"; > reg = <0 0x1001B000 0 0x1000>; > diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts > index 7459ddb6b6f0..7673aa3fa6ae 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts > +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts > @@ -96,6 +96,20 @@ fixed-link { > }; > > &pio { > + spi_flash_pins: spi-flash-pins { > + mux { > + function = "spi"; > + groups = "spi0", "spi0_wp_hold"; Waiting on pinctrl binding: https://patchwork.kernel.org/project/linux-mediatek/patch/20221106080114.7426-2-linux@fw-web.de/ Please resend once merged. Regards, Matthias > + }; > + }; > + > + spic_pins: spic-pins { > + mux { > + function = "spi"; > + groups = "spi1_2"; > + }; > + }; > + > wf_2g_5g_pins: wf-2g-5g-pins { > mux { > function = "wifi"; > @@ -128,6 +142,27 @@ conf { > }; > }; > > +&spi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&spi_flash_pins>; > + cs-gpios = <0>, <0>; > + status = "okay"; > + spi_nand: spi_nand@0 { > + compatible = "spi-nand"; > + reg = <0>; > + spi-max-frequency = <10000000>; > + spi-tx-buswidth = <4>; > + spi-rx-buswidth = <4>; > + }; > +}; > + > +&spi1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&spic_pins>; > + cs-gpios = <0>, <0>; > + status = "okay"; > +}; > + > &uart0 { > status = "okay"; > };
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 6189436fe31d..58f7e6b169bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -55,6 +55,20 @@ switch: switch@0 { }; &pio { + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + uart1_pins: uart1-pins { mux { function = "uart"; @@ -101,6 +115,27 @@ conf { }; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + status = "okay"; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + cs-gpios = <0>, <0>; + status = "okay"; +}; + &switch { ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 226648f48df2..6d881095d933 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -112,6 +112,34 @@ infracfg: infracfg@10001000 { #clock-cells = <1>; }; + spi0: spi@1100a000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100b000 0 0x100>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + topckgen: topckgen@1001b000 { compatible = "mediatek,mt7986-topckgen", "syscon"; reg = <0 0x1001B000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 7459ddb6b6f0..7673aa3fa6ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -96,6 +96,20 @@ fixed-link { }; &pio { + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + wf_2g_5g_pins: wf-2g-5g-pins { mux { function = "wifi"; @@ -128,6 +142,27 @@ conf { }; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + status = "okay"; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + cs-gpios = <0>, <0>; + status = "okay"; +}; + &uart0 { status = "okay"; };