Message ID | 20221031092115.533560-1-pierre.gondois@arm.com |
---|---|
State | Superseded |
Headers | show |
Series | [01/20] arm64: dts: Update cache properties for amd | expand |
diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index 0949acee4728..926da7e1a6ba 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -64,6 +64,7 @@ cpu3: cpu@3 { l2: cache { compatible = "cache"; + cache-level = <2>; }; idle-states {
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> --- arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 + 1 file changed, 1 insertion(+)