@@ -20,6 +20,8 @@
static const char *adsp_clks[ADSP_CLK_MAX] = {
[CLK_TOP_AUDIODSP] = "audiodsp",
[CLK_TOP_ADSP_BUS] = "adsp_bus",
+ [CLK_TOP_MAINPLL_D2_D2] = "mainpll_d2_d2",
+ [CLK_TOP_CLK26M] = "clk26m",
};
int mt8186_adsp_init_clock(struct snd_sof_dev *sdev)
@@ -48,18 +50,36 @@ static int adsp_enable_all_clock(struct snd_sof_dev *sdev)
struct device *dev = sdev->dev;
int ret;
- ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIODSP]);
+ ret = clk_set_parent(priv->clk[CLK_TOP_AUDIODSP], priv->clk[CLK_TOP_CLK26M]);
+ if (ret) {
+ dev_err(dev, "set audiodsp clock fail %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_set_parent(priv->clk[CLK_TOP_ADSP_BUS], priv->clk[CLK_TOP_MAINPLL_D2_D2]);
+ if (ret) {
+ dev_err(dev, "set adsp bus clock fail %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->clk[CLK_TOP_MAINPLL_D2_D2]);
if (ret) {
- dev_err(dev, "%s clk_prepare_enable(audiodsp) fail %d\n",
- __func__, ret);
+ dev_err(dev, "clk_prepare_enable(mainpll_d2_d2) fail %d\n", ret);
return ret;
}
ret = clk_prepare_enable(priv->clk[CLK_TOP_ADSP_BUS]);
if (ret) {
- dev_err(dev, "%s clk_prepare_enable(adsp_bus) fail %d\n",
- __func__, ret);
- clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
+ dev_err(dev, "clk_prepare_enable(adsp_bus) fail %d\n", ret);
+ clk_disable_unprepare(priv->clk[CLK_TOP_MAINPLL_D2_D2]);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIODSP]);
+ if (ret) {
+ dev_err(dev, "clk_prepare_enable(audiodsp) fail %d\n", ret);
+ clk_disable_unprepare(priv->clk[CLK_TOP_MAINPLL_D2_D2]);
+ clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]);
return ret;
}
@@ -70,8 +90,9 @@ static void adsp_disable_all_clock(struct snd_sof_dev *sdev)
{
struct adsp_priv *priv = sdev->pdata->hw_pdata;
- clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]);
clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
+ clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]);
+ clk_disable_unprepare(priv->clk[CLK_TOP_MAINPLL_D2_D2]);
}
int mt8186_adsp_clock_on(struct snd_sof_dev *sdev)
@@ -15,6 +15,8 @@ struct snd_sof_dev;
enum adsp_clk_id {
CLK_TOP_AUDIODSP,
CLK_TOP_ADSP_BUS,
+ CLK_TOP_MAINPLL_D2_D2,
+ CLK_TOP_CLK26M,
ADSP_CLK_MAX
};
Initialize the required clocks for mt8186 ADSP. The ADSP core is expected booting with 26M clock, and using the mainpll_d2_d2 clock for ADSP bus. The enable/disable order of clocks is also revised. The clock should be enabled as mainpll_d2_d2 -> adsp bus -> adsp, and disabled in the reversed order. Fixes: 210b3ab932f7 ("ASoC: SOF: mediatek: Add mt8186 dsp clock support") Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> --- sound/soc/sof/mediatek/mt8186/mt8186-clk.c | 35 +++++++++++++++++----- sound/soc/sof/mediatek/mt8186/mt8186-clk.h | 2 ++ 2 files changed, 30 insertions(+), 7 deletions(-)