| Message ID | 20221028120812.339100-8-robert.foss@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable Display for SM8350 | expand |
On Fri, Oct 28, 2022 at 02:08:10PM +0200, Robert Foss wrote: > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > nodes the display subsystem is configured to support > one DSI output. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++++++++++++++++++++++++++- > 1 file changed, 192 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index b6e44cd3b394..eaa3cdee1860 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include <dt-bindings/interconnect/qcom,sm8350.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,dispcc-sm8350.h> > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > @@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + mdss: mdss@ae00000 { display-subsystem@ae00000 please. > + compatible = "qcom,sm8350-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + status = "ok"; You want "disabled" here, and then "okay" in the .dts. > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss_mdp: mdp@ae01000 { display-controller@ae01000 please. > + compatible = "qcom,sm8350-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + iommus = <&apps_smmu 0x820 0x402>; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + status = "ok"; "okay", but this is the default, so you can skip it in the .dtsi > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + > + mdp_opp_table: mdp-opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-345000000 { > + opp-hz = /bits/ 64 <345000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-460000000 { > + opp-hz = /bits/ 64 <460000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + dsi0: dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + phys = <&dsi0_phy>; > + phy-names = "dsi"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi0_phy: dsi-phy@ae94400 { > + compatible = "qcom,dsi-phy-5nm-8350"; > + reg = <0 0x0ae94400 0 0x200>, > + <0 0x0ae94600 0 0x280>, > + <0 0x0ae94900 0 0x260>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + > + dsi_opp_table: dsi-opp-table { > + compatible = "operating-points-v2"; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + }; > + > dispcc: clock-controller@af00000 { > compatible = "qcom,sm8350-dispcc"; > reg = <0 0x0af00000 0 0x10000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > - <0>, > - <0>, > - <0>, > - <0>, > + <&dsi0_phy 0>, <&dsi0_phy 1>, > + <0>, <0>, > <0>, > <0>; > clock-names = "bi_tcxo", > @@ -2557,6 +2744,7 @@ dispcc: clock-controller@af00000 { > #power-domain-cells = <1>; > > power-domains = <&rpmhpd SM8350_MMCX>; > + required-opps = <&rpmhpd_opp_turbo>; That seems a little bit aggressive, is the opp-based voting from within the mdss/dpu not sufficient? Regards, Bjorn > }; > > adsp: remoteproc@17300000 { > -- > 2.34.1 >
On 28/10/2022 08:08, Robert Foss wrote: > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > nodes the display subsystem is configured to support > one DSI output. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++++++++++++++++++++++++++- > 1 file changed, 192 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index b6e44cd3b394..eaa3cdee1860 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include <dt-bindings/interconnect/qcom,sm8350.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,dispcc-sm8350.h> > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > @@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + mdss: mdss@ae00000 { > + compatible = "qcom,sm8350-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "nrt_bus", "core"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + status = "ok"; No need for this. > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + mdss_mdp: mdp@ae01000 { Node name: display-controller > + compatible = "qcom,sm8350-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + iommus = <&apps_smmu 0x820 0x402>; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + status = "ok"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + > + mdp_opp_table: mdp-opp-table { I have doubts that it passes dtbs_checks... opp-table > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-345000000 { > + opp-hz = /bits/ 64 <345000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-460000000 { > + opp-hz = /bits/ 64 <460000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + dsi0: dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmhpd SM8350_MMCX>; > + > + phys = <&dsi0_phy>; > + phy-names = "dsi"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi0_phy: dsi-phy@ae94400 { Just "phy". I think Dmitry was renaming all of these. > + compatible = "qcom,dsi-phy-5nm-8350"; > + reg = <0 0x0ae94400 0 0x200>, > + <0 0x0ae94600 0 0x280>, > + <0 0x0ae94900 0 0x260>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + > + dsi_opp_table: dsi-opp-table { opp-table Run `make dtbs_check` Best regards, Krzysztof
On Sat, 29 Oct 2022 at 00:01, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > On 28/10/2022 08:08, Robert Foss wrote: > > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these > > nodes the display subsystem is configured to support > > one DSI output. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++++++++++++++++++++++++++- > > 1 file changed, 192 insertions(+), 4 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > index b6e44cd3b394..eaa3cdee1860 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > @@ -3,6 +3,7 @@ > > * Copyright (c) 2020, Linaro Limited > > */ > > > > +#include <dt-bindings/interconnect/qcom,sm8350.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > #include <dt-bindings/clock/qcom,dispcc-sm8350.h> > > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > > @@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a800000 { > > }; > > }; > > > > + mdss: mdss@ae00000 { > > + compatible = "qcom,sm8350-mdss"; > > + reg = <0 0x0ae00000 0 0x1000>; > > + reg-names = "mdss"; > > + > > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > > + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; > > + interconnect-names = "mdp0-mem", "mdp1-mem"; > > + > > + power-domains = <&dispcc MDSS_GDSC>; > > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > > + > > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > > + <&gcc GCC_DISP_HF_AXI_CLK>, > > + <&gcc GCC_DISP_SF_AXI_CLK>, > > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > > + clock-names = "iface", "bus", "nrt_bus", "core"; > > + > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + > > + status = "ok"; > > No need for this. Ack, I'll switch to disabled. > > > + > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + mdss_mdp: mdp@ae01000 { > > Node name: display-controller Ack. > > + compatible = "qcom,sm8350-dpu"; > > + reg = <0 0x0ae01000 0 0x8f000>, > > + <0 0x0aeb0000 0 0x2008>; > > + reg-names = "mdp", "vbif"; > > + iommus = <&apps_smmu 0x820 0x402>; > > + > > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > > + <&gcc GCC_DISP_SF_AXI_CLK>, > > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > > + clock-names = "bus", > > + "nrt_bus", > > + "iface", > > + "lut", > > + "core", > > + "vsync"; > > + > > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > > + assigned-clock-rates = <19200000>; > > + > > + operating-points-v2 = <&mdp_opp_table>; > > + power-domains = <&rpmhpd SM8350_MMCX>; > > + > > + interrupt-parent = <&mdss>; > > + interrupts = <0>; > > + > > + status = "ok"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + dpu_intf1_out: endpoint { > > + remote-endpoint = <&dsi0_in>; > > + }; > > + }; > > + }; > > + > > + mdp_opp_table: mdp-opp-table { > > I have doubts that it passes dtbs_checks... opp-table Ack. > > > + compatible = "operating-points-v2"; > > + > > + opp-200000000 { > > + opp-hz = /bits/ 64 <200000000>; > > + required-opps = <&rpmhpd_opp_low_svs>; > > + }; > > + > > + opp-300000000 { > > + opp-hz = /bits/ 64 <300000000>; > > + required-opps = <&rpmhpd_opp_svs>; > > + }; > > + > > + opp-345000000 { > > + opp-hz = /bits/ 64 <345000000>; > > + required-opps = <&rpmhpd_opp_svs_l1>; > > + }; > > + > > + opp-460000000 { > > + opp-hz = /bits/ 64 <460000000>; > > + required-opps = <&rpmhpd_opp_nom>; > > + }; > > + }; > > + }; > > + > > + dsi0: dsi@ae94000 { > > + compatible = "qcom,mdss-dsi-ctrl"; > > + reg = <0 0x0ae94000 0 0x400>; > > + reg-names = "dsi_ctrl"; > > + > > + interrupt-parent = <&mdss>; > > + interrupts = <4>; > > + > > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > > + <&gcc GCC_DISP_HF_AXI_CLK>; > > + clock-names = "byte", > > + "byte_intf", > > + "pixel", > > + "core", > > + "iface", > > + "bus"; > > + > > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > > + assigned-clock-parents = <&dsi0_phy 0>, > > + <&dsi0_phy 1>; > > + > > + operating-points-v2 = <&dsi_opp_table>; > > + power-domains = <&rpmhpd SM8350_MMCX>; > > + > > + phys = <&dsi0_phy>; > > + phy-names = "dsi"; > > + > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + dsi0_in: endpoint { > > + remote-endpoint = <&dpu_intf1_out>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + dsi0_out: endpoint { > > + }; > > + }; > > + }; > > + }; > > + > > + dsi0_phy: dsi-phy@ae94400 { > > Just "phy". I think Dmitry was renaming all of these. Ack. > > > + compatible = "qcom,dsi-phy-5nm-8350"; > > + reg = <0 0x0ae94400 0 0x200>, > > + <0 0x0ae94600 0 0x280>, > > + <0 0x0ae94900 0 0x260>; > > + reg-names = "dsi_phy", > > + "dsi_phy_lane", > > + "dsi_pll"; > > + > > + #clock-cells = <1>; > > + #phy-cells = <0>; > > + > > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > > + <&rpmhcc RPMH_CXO_CLK>; > > + clock-names = "iface", "ref"; > > + > > + status = "disabled"; > > + > > + dsi_opp_table: dsi-opp-table { > > opp-table Ack > > Run `make dtbs_check` I had a look after fixing the above and I'm seeing some other issues. Due to the dts/dt-binding rework that Dmitry is doing, I'll leave some warnings, which can be addressed once the rework changes have landed. > > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index b6e44cd3b394..eaa3cdee1860 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ +#include <dt-bindings/interconnect/qcom,sm8350.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,dispcc-sm8350.h> #include <dt-bindings/clock/qcom,gcc-sm8350.h> @@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a800000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sm8350-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + status = "ok"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + iommus = <&apps_smmu 0x820 0x402>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + status = "ok"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, + <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8350"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sm8350-dispcc"; reg = <0 0x0af00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <0>, - <0>, - <0>, - <0>, + <&dsi0_phy 0>, <&dsi0_phy 1>, + <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", @@ -2557,6 +2744,7 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; power-domains = <&rpmhpd SM8350_MMCX>; + required-opps = <&rpmhpd_opp_turbo>; }; adsp: remoteproc@17300000 {
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these nodes the display subsystem is configured to support one DSI output. Signed-off-by: Robert Foss <robert.foss@linaro.org> --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++++++++++++++++++++++++++- 1 file changed, 192 insertions(+), 4 deletions(-)