| Message ID | 20221024151444.3208225-1-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/2] drm/msm: remove duplicated code from a6xx_create_address_space | expand |
On 24/10/2022 19:12, Rob Clark wrote: > On Mon, Oct 24, 2022 at 8:14 AM Dmitry Baryshkov > <dmitry.baryshkov@linaro.org> wrote: >> >> The function a6xx_create_address_space() is mostly a copy of >> adreno_iommu_create_address_space() with added quirk setting. Reuse the >> original function to do the work, while introducing the wrapper to set >> the quirk. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 ++++--------------------- >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 ++-- >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- >> drivers/gpu/drm/msm/msm_iommu.c | 7 ++++++ >> drivers/gpu/drm/msm/msm_mmu.h | 1 + >> 5 files changed, 15 insertions(+), 30 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index fdc578016e0b..7640f5b960d6 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -1786,41 +1786,18 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) >> { >> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); >> struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); >> - struct iommu_domain *iommu; >> - struct msm_mmu *mmu; >> struct msm_gem_address_space *aspace; >> - u64 start, size; >> >> - iommu = iommu_domain_alloc(&platform_bus_type); >> - if (!iommu) >> - return NULL; >> + aspace = adreno_iommu_create_address_space(gpu, pdev); >> + if (IS_ERR_OR_NULL(aspace)) >> + return ERR_CAST(aspace); >> >> /* >> * This allows GPU to set the bus attributes required to use system >> * cache on behalf of the iommu page table walker. >> */ >> if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) >> - adreno_set_llc_attributes(iommu); >> - >> - mmu = msm_iommu_new(&pdev->dev, iommu); >> - if (IS_ERR(mmu)) { >> - iommu_domain_free(iommu); >> - return ERR_CAST(mmu); >> - } >> - >> - /* >> - * Use the aperture start or SZ_16M, whichever is greater. This will >> - * ensure that we align with the allocated pagetable range while still >> - * allowing room in the lower 32 bits for GMEM and whatnot >> - */ >> - start = max_t(u64, SZ_16M, iommu->geometry.aperture_start); >> - size = iommu->geometry.aperture_end - start + 1; >> - >> - aspace = msm_gem_address_space_create(mmu, "gpu", >> - start & GENMASK_ULL(48, 0), size); >> - >> - if (IS_ERR(aspace) && !IS_ERR(mmu)) >> - mmu->funcs->destroy(mmu); >> + adreno_set_llc_attributes(aspace->mmu); >> >> return aspace; >> } >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >> index 382fb7f9e497..ed26b8dfc789 100644 >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >> @@ -191,9 +191,9 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) >> return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); >> } >> >> -void adreno_set_llc_attributes(struct iommu_domain *iommu) >> +void adreno_set_llc_attributes(struct msm_mmu *mmu) >> { >> - iommu_set_pgtable_quirks(iommu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA); >> + msm_iommu_set_pgtable_quirks(mmu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA); >> } > > This won't actually work.. looking at the arm-smmu code, the quirks > need to be set before attaching the device. But there is an even > simpler way, just pass the quirks bitmask to msm_iommu_new() and get > rid of adreno_set_llc_attributes(), and msm_iommu_set_pgtable_quirks() Ack, thanks for the idea! > > BR, > -R > >> >> struct msm_gem_address_space * >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> index e7adc5c632d0..723729e463e8 100644 >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> @@ -338,7 +338,7 @@ struct msm_gem_address_space * >> adreno_iommu_create_address_space(struct msm_gpu *gpu, >> struct platform_device *pdev); >> >> -void adreno_set_llc_attributes(struct iommu_domain *iommu); >> +void adreno_set_llc_attributes(struct msm_mmu *mmu); >> >> int adreno_read_speedbin(struct device *dev, u32 *speedbin); >> >> diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c >> index 5577cea7c009..768ab71cc43e 100644 >> --- a/drivers/gpu/drm/msm/msm_iommu.c >> +++ b/drivers/gpu/drm/msm/msm_iommu.c >> @@ -186,6 +186,13 @@ int msm_iommu_pagetable_params(struct msm_mmu *mmu, >> return 0; >> } >> >> +int msm_iommu_set_pgtable_quirks(struct msm_mmu *mmu, unsigned long quirk) >> +{ >> + struct msm_iommu *iommu = to_msm_iommu(mmu); >> + >> + return iommu_set_pgtable_quirks(iommu->domain, quirk); >> +} >> + >> static const struct msm_mmu_funcs pagetable_funcs = { >> .map = msm_iommu_pagetable_map, >> .unmap = msm_iommu_pagetable_unmap, >> diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h >> index de158e1bf765..d968d9f8e19c 100644 >> --- a/drivers/gpu/drm/msm/msm_mmu.h >> +++ b/drivers/gpu/drm/msm/msm_mmu.h >> @@ -58,5 +58,6 @@ void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, >> >> int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr, >> int *asid); >> +int msm_iommu_set_pgtable_quirks(struct msm_mmu *mmu, unsigned long quirk); >> >> #endif /* __MSM_MMU_H__ */ >> -- >> 2.35.1 >>
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index fdc578016e0b..7640f5b960d6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1786,41 +1786,18 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - struct iommu_domain *iommu; - struct msm_mmu *mmu; struct msm_gem_address_space *aspace; - u64 start, size; - iommu = iommu_domain_alloc(&platform_bus_type); - if (!iommu) - return NULL; + aspace = adreno_iommu_create_address_space(gpu, pdev); + if (IS_ERR_OR_NULL(aspace)) + return ERR_CAST(aspace); /* * This allows GPU to set the bus attributes required to use system * cache on behalf of the iommu page table walker. */ if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) - adreno_set_llc_attributes(iommu); - - mmu = msm_iommu_new(&pdev->dev, iommu); - if (IS_ERR(mmu)) { - iommu_domain_free(iommu); - return ERR_CAST(mmu); - } - - /* - * Use the aperture start or SZ_16M, whichever is greater. This will - * ensure that we align with the allocated pagetable range while still - * allowing room in the lower 32 bits for GMEM and whatnot - */ - start = max_t(u64, SZ_16M, iommu->geometry.aperture_start); - size = iommu->geometry.aperture_end - start + 1; - - aspace = msm_gem_address_space_create(mmu, "gpu", - start & GENMASK_ULL(48, 0), size); - - if (IS_ERR(aspace) && !IS_ERR(mmu)) - mmu->funcs->destroy(mmu); + adreno_set_llc_attributes(aspace->mmu); return aspace; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 382fb7f9e497..ed26b8dfc789 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -191,9 +191,9 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); } -void adreno_set_llc_attributes(struct iommu_domain *iommu) +void adreno_set_llc_attributes(struct msm_mmu *mmu) { - iommu_set_pgtable_quirks(iommu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA); + msm_iommu_set_pgtable_quirks(mmu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA); } struct msm_gem_address_space * diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index e7adc5c632d0..723729e463e8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -338,7 +338,7 @@ struct msm_gem_address_space * adreno_iommu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev); -void adreno_set_llc_attributes(struct iommu_domain *iommu); +void adreno_set_llc_attributes(struct msm_mmu *mmu); int adreno_read_speedbin(struct device *dev, u32 *speedbin); diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 5577cea7c009..768ab71cc43e 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -186,6 +186,13 @@ int msm_iommu_pagetable_params(struct msm_mmu *mmu, return 0; } +int msm_iommu_set_pgtable_quirks(struct msm_mmu *mmu, unsigned long quirk) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + + return iommu_set_pgtable_quirks(iommu->domain, quirk); +} + static const struct msm_mmu_funcs pagetable_funcs = { .map = msm_iommu_pagetable_map, .unmap = msm_iommu_pagetable_unmap, diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index de158e1bf765..d968d9f8e19c 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -58,5 +58,6 @@ void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr, int *asid); +int msm_iommu_set_pgtable_quirks(struct msm_mmu *mmu, unsigned long quirk); #endif /* __MSM_MMU_H__ */
The function a6xx_create_address_space() is mostly a copy of adreno_iommu_create_address_space() with added quirk setting. Reuse the original function to do the work, while introducing the wrapper to set the quirk. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 ++++--------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- drivers/gpu/drm/msm/msm_iommu.c | 7 ++++++ drivers/gpu/drm/msm/msm_mmu.h | 1 + 5 files changed, 15 insertions(+), 30 deletions(-)