@@ -141,6 +141,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
/**
* struct zynqmp_qspi - Defines qspi driver instance
+ * @ctlr: Pointer to the spi controller information
* @regs: Virtual address of the QSPI controller registers
* @refclk: Pointer to the peripheral clock
* @pclk: Pointer to the APB clock
@@ -157,6 +158,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
* @genfifoentry: Used for storing the genfifoentry instruction.
* @mode: Defines the mode in which QSPI is operating
* @data_completion: completion structure
+ * @op_lock: Operational lock
*/
struct zynqmp_qspi {
struct spi_controller *ctlr;
@@ -739,6 +741,8 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
/**
* zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
* @xqspi: xqspi is a pointer to the GQSPI instance.
+ *
+ * Return: 0 on success; error value otherwise.
*/
static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
{
@@ -823,6 +827,8 @@ static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
* @rx_nbits: Receive buswidth.
* @genfifoentry: genfifoentry is pointer to the variable in which
* GENFIFO mask is returned to calling function
+ *
+ * Return: 0 on success; error value otherwise.
*/
static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
u32 genfifoentry)