| Message ID | 1454522458-29643-1-git-send-email-will.deacon@arm.com |
|---|---|
| State | Accepted |
| Commit | 4aff7b854611d91c5fefb1553eb4c328123095ae |
| Headers | show |
On Wed, Feb 03, 2016 at 06:00:58PM +0000, Will Deacon wrote: > The arm,gic-v3 binding was written with good intentions and doesn't > enforce interrupt-cells to be 3, therefore making it easy to extend > the irq description in future if necessary: > > > Cells 4 and beyond are reserved for future use. > > Unfortunately, this sentence is immediately followed up with: > > > When the 1st cell has a value of 0 or 1, cells 4 and beyond act as > > padding, and may be ignored. It is recommended that padding cells > > have a value of 0. The initial intention of this was to allow for new, longer entries which were identified by a new value in cell 1. Regardless, I agree that it should be a requirement that padding cells must be zero. > Consequently, any extensions to the PPI or SPI interrupt specifiers must > be able to work with random crap from legacy DTs, effectively > necessitating a new interrupt type in the first cell. Sigh. I'm not sure that's true if we allocate a new value for the 1st cell for "extended" PPI or SPI interrupt-sepcficiers (which presumably add restrictions). That would also allow old kernels to safely skip such interrupts rather than mis-parsing them. > This patch fixes the text so that additional, reserved cells are > required to be zero. This looks like a reasonable thing to require and > is already satisifed by the .dts files in-tree. > > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Marc Zyngier <marc.zyngier@arm.com> > Signed-off-by: Will Deacon <will.deacon@arm.com> This patch itself makes sense, so FWIW: Acked-by: Mark Rutland <mark.rutland@arm.com> Any proposed extention to the binding requires its own discussion. Thanks, Mark. > --- > .../devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt > index 7803e77d85cb..007a5b46256a 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt > +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt > @@ -24,9 +24,8 @@ Main node required properties: > 1 = edge triggered > 4 = level triggered > > - Cells 4 and beyond are reserved for future use. When the 1st cell > - has a value of 0 or 1, cells 4 and beyond act as padding, and may be > - ignored. It is recommended that padding cells have a value of 0. > + Cells 4 and beyond are reserved for future use and must have a value > + of 0 if present. > > - reg : Specifies base physical address(s) and size of the GIC > registers, in the following order: > -- > 2.1.4 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, Feb 03, 2016 at 06:20:54PM +0000, Mark Rutland wrote: > On Wed, Feb 03, 2016 at 06:00:58PM +0000, Will Deacon wrote: > > Consequently, any extensions to the PPI or SPI interrupt specifiers must > > be able to work with random crap from legacy DTs, effectively > > necessitating a new interrupt type in the first cell. Sigh. > > I'm not sure that's true if we allocate a new value for the 1st cell for > "extended" PPI or SPI interrupt-sepcficiers (which presumably add > restrictions). That would also allow old kernels to safely skip such > interrupts rather than mis-parsing them. Right, that's what I said :) > > This patch fixes the text so that additional, reserved cells are > > required to be zero. This looks like a reasonable thing to require and > > is already satisifed by the .dts files in-tree. > > > > Cc: Mark Rutland <mark.rutland@arm.com> > > Cc: Marc Zyngier <marc.zyngier@arm.com> > > Signed-off-by: Will Deacon <will.deacon@arm.com> > > This patch itself makes sense, so FWIW: > > Acked-by: Mark Rutland <mark.rutland@arm.com> > > Any proposed extention to the binding requires its own discussion. Yup. Marc -- can you queue this please? Will -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 7803e77d85cb..007a5b46256a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -24,9 +24,8 @@ Main node required properties: 1 = edge triggered 4 = level triggered - Cells 4 and beyond are reserved for future use. When the 1st cell - has a value of 0 or 1, cells 4 and beyond act as padding, and may be - ignored. It is recommended that padding cells have a value of 0. + Cells 4 and beyond are reserved for future use and must have a value + of 0 if present. - reg : Specifies base physical address(s) and size of the GIC registers, in the following order: