Message ID | 20220926091503.199474-1-chenweilong@huawei.com |
---|---|
State | Superseded |
Headers | show |
Series | [next,v3] i2c: hisi: Add support to get clock frequency from clock property | expand |
On Mon, Sep 26, 2022 at 05:15:03PM +0800, Weilong Chen wrote: > Support the driver to obtain clock information by clk_rate or > clock property. Find clock first, if not, fall back to clk_rate. This commit message describes what the patch does. But it misses the explanation why this needs to be done. Could you add this information, please? Patch itself looks also good to me. > > Signed-off-by: Weilong Chen <chenweilong@huawei.com> > Acked-by: Yicong Yang <yangyicong@hisilicon.com>
On 2022/9/29 3:52, Wolfram Sang wrote: > On Mon, Sep 26, 2022 at 05:15:03PM +0800, Weilong Chen wrote: >> Support the driver to obtain clock information by clk_rate or >> clock property. Find clock first, if not, fall back to clk_rate. > This commit message describes what the patch does. But it misses the > explanation why this needs to be done. Could you add this information, > please? Patch itself looks also good to me. OK, I'll update it. Thanks. >> Signed-off-by: Weilong Chen <chenweilong@huawei.com> >> Acked-by: Yicong Yang <yangyicong@hisilicon.com>
diff --git a/drivers/i2c/busses/i2c-hisi.c b/drivers/i2c/busses/i2c-hisi.c index 67031024217c..e4b0ebe54f6f 100644 --- a/drivers/i2c/busses/i2c-hisi.c +++ b/drivers/i2c/busses/i2c-hisi.c @@ -8,6 +8,7 @@ #include <linux/acpi.h> #include <linux/bits.h> #include <linux/bitfield.h> +#include <linux/clk.h> #include <linux/completion.h> #include <linux/i2c.h> #include <linux/interrupt.h> @@ -90,6 +91,7 @@ struct hisi_i2c_controller { struct i2c_adapter adapter; void __iomem *iobase; struct device *dev; + struct clk *clk; int irq; /* Intermediates for recording the transfer process */ @@ -456,10 +458,15 @@ static int hisi_i2c_probe(struct platform_device *pdev) return ret; } - ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); - if (ret) { - dev_err(dev, "failed to get clock frequency, ret = %d\n", ret); - return ret; + ctlr->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); + if (IS_ERR_OR_NULL(ctlr->clk)) { + ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); + if (ret) { + dev_err(dev, "failed to get clock frequency, ret = %d\n", ret); + return ret; + } + } else { + clk_rate_hz = clk_get_rate(ctlr->clk); } ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ);