Message ID | 20220922163536.1096175-29-peter.maydell@linaro.org |
---|---|
State | Accepted |
Commit | 7650c8fe520c67c3b36f6962c4ad990f56ad40b8 |
Headers | show
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Series |
[PULL,01/39] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
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diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 5b0b4d96242..dcd021af668 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -567,8 +567,8 @@ static void ics_reset_irq(ICSIRQState *irq) static void ics_reset(DeviceState *dev) { ICSState *ics = ICS(dev); + g_autofree uint8_t *flags = g_malloc(ics->nr_irqs); int i; - uint8_t flags[ics->nr_irqs]; for (i = 0; i < ics->nr_irqs; i++) { flags[i] = ics->irqs[i].flags;