| Message ID | 20220913142818.7802-2-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/m68k: fix two writes to %sr | expand |
Le 13/09/2022 à 16:28, Richard Henderson a écrit : > First, we were writing to the entire SR register, instead > of only the flags portion. Second, we were not clearing C > as per the documentation (X was cleared via the 0xf mask). > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/m68k/translate.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/m68k/translate.c b/target/m68k/translate.c > index 5098f7e570..87044382c3 100644 > --- a/target/m68k/translate.c > +++ b/target/m68k/translate.c > @@ -5892,8 +5892,10 @@ DISAS_INSN(from_mext) > DISAS_INSN(macsr_to_ccr) > { > TCGv tmp = tcg_temp_new(); > - tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); > - gen_helper_set_sr(cpu_env, tmp); > + > + /* Note that X and C are always cleared. */ > + tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V); > + gen_helper_set_ccr(cpu_env, tmp); > tcg_temp_free(tmp); > set_cc_op(s, CC_OP_FLAGS); > } Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Le 13/09/2022 à 16:28, Richard Henderson a écrit : > First, we were writing to the entire SR register, instead > of only the flags portion. Second, we were not clearing C > as per the documentation (X was cleared via the 0xf mask). > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/m68k/translate.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/m68k/translate.c b/target/m68k/translate.c > index 5098f7e570..87044382c3 100644 > --- a/target/m68k/translate.c > +++ b/target/m68k/translate.c > @@ -5892,8 +5892,10 @@ DISAS_INSN(from_mext) > DISAS_INSN(macsr_to_ccr) > { > TCGv tmp = tcg_temp_new(); > - tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); > - gen_helper_set_sr(cpu_env, tmp); > + > + /* Note that X and C are always cleared. */ > + tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V); > + gen_helper_set_ccr(cpu_env, tmp); > tcg_temp_free(tmp); > set_cc_op(s, CC_OP_FLAGS); > } Applied to my m68k-for-7.2 branch Thanks, Laurent
diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 5098f7e570..87044382c3 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5892,8 +5892,10 @@ DISAS_INSN(from_mext) DISAS_INSN(macsr_to_ccr) { TCGv tmp = tcg_temp_new(); - tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); - gen_helper_set_sr(cpu_env, tmp); + + /* Note that X and C are always cleared. */ + tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V); + gen_helper_set_ccr(cpu_env, tmp); tcg_temp_free(tmp); set_cc_op(s, CC_OP_FLAGS); }
First, we were writing to the entire SR register, instead of only the flags portion. Second, we were not clearing C as per the documentation (X was cleared via the 0xf mask). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/m68k/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)