| Message ID | 20220912071511.1385-9-hayashi.kunihiko@socionext.com |
|---|---|
| State | Accepted |
| Commit | 86b20827becef3fb69c41fb8327cce7511956783 |
| Headers | show |
| Series | Update UniPhier armv7 devicetree | expand |
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 64cdd0c62e55..c3e431b3f643 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -620,8 +620,7 @@ usb1_ssphy0: ss-phy@380 { }; pcie_ep: pcie-ep@66000000 { - compatible = "socionext,uniphier-pro5-pcie-ep", - "snps,dw-pcie-ep"; + compatible = "socionext,uniphier-pro5-pcie-ep"; status = "disabled"; reg-names = "dbi", "dbi2", "link", "addr_space"; reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
The generic platform driver pcie-designware-plat.c doesn't work for UniPhier PCIe endpoint controller, because the controller has some necessary initialization sequence for the controller-specific logic. Currently the controller doesn't use "snps,dw-pcie-ep" compatible, so this is no longer needed. Remove the compatible string from the pcie-ep node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- arch/arm/boot/dts/uniphier-pro5.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)