diff mbox series

[v3,4/9] phy: qcom-qmp-pcie: split PHY programming to separate functions

Message ID 20220909091433.3715981-5-dmitry.baryshkov@linaro.org
State New
Headers show
Series PCI: qcom: Support using the same PHY for both RC and EP | expand

Commit Message

Dmitry Baryshkov Sept. 9, 2022, 9:14 a.m. UTC 
Split the code using PHY programming tables into separate functions,
which take a single struct qmp_phy_cfg_tables instance.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 92 +++++++++++++-----------
 1 file changed, 49 insertions(+), 43 deletions(-)
diff mbox series

Patch

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index ca8dffaf1081..5250c3f06c89 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1949,15 +1949,54 @@  static void qcom_qmp_phy_pcie_configure(void __iomem *base,
 	qcom_qmp_phy_pcie_configure_lane(base, regs, tbl, num, 0xff);
 }
 
-static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy)
+static void qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)
 {
 	const struct qmp_phy_cfg *cfg = qphy->cfg;
 	void __iomem *serdes = qphy->serdes;
 
-	qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->main.serdes_tbl, cfg->main.serdes_tbl_num);
-	qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->secondary.serdes_tbl, cfg->secondary.serdes_tbl_num);
+	if (!tables)
+		return;
 
-	return 0;
+	qcom_qmp_phy_pcie_configure(serdes, cfg->regs, tables->serdes_tbl, tables->serdes_tbl_num);
+}
+
+static void qcom_qmp_phy_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)
+{
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
+	void __iomem *tx = qphy->tx;
+	void __iomem *rx = qphy->rx;
+
+	if (!tables)
+		return;
+
+	qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
+					 tables->tx_tbl, tables->tx_tbl_num, 1);
+
+	if (cfg->is_dual_lane_phy)
+		qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
+						 tables->tx_tbl, tables->tx_tbl_num, 2);
+
+	qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
+					 tables->rx_tbl, tables->rx_tbl_num, 1);
+	if (cfg->is_dual_lane_phy)
+		qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
+						 tables->rx_tbl, tables->rx_tbl_num, 2);
+}
+
+static void qcom_qmp_phy_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)
+{
+	const struct qmp_phy_cfg *cfg = qphy->cfg;
+	void __iomem *pcs = qphy->pcs;
+	void __iomem *pcs_misc = qphy->pcs_misc;
+
+	if (!tables)
+		return;
+
+	qcom_qmp_phy_pcie_configure(pcs, cfg->regs,
+				    tables->pcs_tbl, tables->pcs_tbl_num);
+	qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs,
+				    tables->pcs_misc_tbl,
+				    tables->pcs_misc_tbl_num);
 }
 
 static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy)
@@ -2041,15 +2080,13 @@  static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
 	struct qmp_phy *qphy = phy_get_drvdata(phy);
 	struct qcom_qmp *qmp = qphy->qmp;
 	const struct qmp_phy_cfg *cfg = qphy->cfg;
-	void __iomem *tx = qphy->tx;
-	void __iomem *rx = qphy->rx;
 	void __iomem *pcs = qphy->pcs;
-	void __iomem *pcs_misc = qphy->pcs_misc;
 	void __iomem *status;
 	unsigned int mask, val, ready;
 	int ret;
 
-	qcom_qmp_phy_pcie_serdes_init(qphy);
+	qcom_qmp_phy_pcie_serdes_init(qphy, &cfg->main);
+	qcom_qmp_phy_pcie_serdes_init(qphy, &cfg->secondary);
 
 	ret = clk_prepare_enable(qphy->pipe_clk);
 	if (ret) {
@@ -2058,42 +2095,11 @@  static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
 	}
 
 	/* Tx, Rx, and PCS configurations */
-	qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
-					 cfg->main.tx_tbl, cfg->main.tx_tbl_num, 1);
-	qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
-					 cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 1);
+	qcom_qmp_phy_pcie_lanes_init(qphy, &cfg->main);
+	qcom_qmp_phy_pcie_lanes_init(qphy, &cfg->secondary);
 
-	/* Configuration for other LANE for USB-DP combo PHY */
-	if (cfg->is_dual_lane_phy) {
-		qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
-						 cfg->main.tx_tbl, cfg->main.tx_tbl_num, 2);
-		qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
-						 cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 2);
-	}
-
-	qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
-					 cfg->main.rx_tbl, cfg->main.rx_tbl_num, 1);
-	qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
-					 cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 1);
-
-	if (cfg->is_dual_lane_phy) {
-		qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
-						 cfg->main.rx_tbl, cfg->main.rx_tbl_num, 2);
-		qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
-						 cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 2);
-	}
-
-	qcom_qmp_phy_pcie_configure(pcs, cfg->regs,
-				    cfg->main.pcs_tbl, cfg->main.pcs_tbl_num);
-	qcom_qmp_phy_pcie_configure(pcs, cfg->regs,
-				    cfg->secondary.pcs_tbl, cfg->secondary.pcs_tbl_num);
-
-	qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs,
-				    cfg->main.pcs_misc_tbl,
-				    cfg->main.pcs_misc_tbl_num);
-	qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs,
-				    cfg->secondary.pcs_misc_tbl,
-				    cfg->secondary.pcs_misc_tbl_num);
+	qcom_qmp_phy_pcie_pcs_init(qphy, &cfg->main);
+	qcom_qmp_phy_pcie_pcs_init(qphy, &cfg->secondary);
 
 	/*
 	 * Pull out PHY from POWER DOWN state.