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[next,v3,2/2] dt-bindings: i2c: add entry for hisilicon,hisi-i2c

Message ID 20220908025701.330210-2-chenweilong@huawei.com
State Superseded
Headers show
Series None | expand

Commit Message

Weilong Chen Sept. 8, 2022, 2:57 a.m. UTC 
Add the new compatible for HiSilicon common i2c.

Signed-off-by: Weilong Chen <chenweilong@huawei.com>
---
 .../bindings/i2c/hisilicon,hisi-i2c.yaml      | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/hisilicon,hisi-i2c.yaml
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Patch

diff --git a/Documentation/devicetree/bindings/i2c/hisilicon,hisi-i2c.yaml b/Documentation/devicetree/bindings/i2c/hisilicon,hisi-i2c.yaml
new file mode 100644
index 000000000000..19d535f4a79e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/hisilicon,hisi-i2c.yaml
@@ -0,0 +1,68 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/i2c/hisilicon,hisi-i2c.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: HiSilicon common IIC controller Device Tree Bindings
+
+maintainers:
+  - yangyicong@huawei.com
+
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+  compatible:
+    const: hisilicon,hisi-i2c
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clk_rate:
+    default: 0xEE6B280
+
+  clock-frequency:
+    default: 400000
+
+  i2c-sda-falling-time-ns:
+    default: 343
+
+  i2c-scl-falling-time-ns:
+    default: 203
+
+  i2c-sda-hold-time-ns:
+    default: 0x33E
+
+  i2c-scl-rising-time-ns:
+    default: 365
+
+  i2c-digital-filter-width-ns:
+    default: 0
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    i2c1: i2c@5038B0000{
+      compatible = "hisilicon,hisi-i2c";
+      #address-cells = <1>;
+      #size-cells = <0>;
+      reg = <0x5 0x038B0000 0 0x10000>;
+      interrupts = <0x0 120 0x4>;
+      i2c-sda-falling-time-ns = <56>;
+      i2c-scl-falling-time-ns = <56>;
+      i2c-sda-hold-time-ns = <56>;
+      i2c-scl-rising-time-ns = <56>;
+      i2c-digital-filter-width-ns = <0x0>;
+      clk_rate = <0x0 0xEE6B280>;
+      clock-frequency = <400000>;
+    };