| Message ID | 1662550553-28933-1-git-send-email-quic_rajeevny@quicinc.com |
|---|---|
| State | Accepted |
| Commit | 80edac18ac173f0f0130c2164f75ddadcd68fa7f |
| Headers | show |
| Series | [v1] arm64: dts: qcom: sc7280: assign DSI clock source parents | expand |
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 50c3d79..a80aa64 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3650,6 +3650,9 @@ "iface", "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; + operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7280_CX>;
Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- This change is needed after the refactor done by the patch [2] (drm/msm/dsi: stop setting clock parents manually) of series [1], to fix the DSI pixel clock set rate error: dsi_link_clk_set_rate_6g: Failed to set rate pixel clk, -22 msm_dsi_host_power_on: failed to enable link clocks. ret=-22 [1] https://github.com/torvalds/linux/commit/9b077c1581cf57206f5f7788ea569e8fae0719a7 [2] https://lore.kernel.org/all/20210709210729.953114-1-dmitry.baryshkov@linaro.org/ arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ 1 file changed, 3 insertions(+)