@@ -10,6 +10,8 @@
/dts-v1/;
+#include <dt-bindings/phy/phy.h>
+
#include "fsl-ls1046a.dtsi"
/ {
@@ -26,8 +28,110 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ clocks {
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <156250000>;
+ };
+ };
};
+&serdes1 {
+ clocks = <&clk_100mhz>, <&clk_156mhz>;
+ clock-names = "ref0", "ref1";
+ status = "okay";
+
+ /*
+ * XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane numbers and pin
+ * numbers are _reversed_. In addition, the PCCR documentation is
+ * _inconsistent_ in its usage of these terms!
+ *
+ * PCCR "Lane 0" refers to...
+ * ==== =====================
+ * 0 Lane A
+ * 2 Lane A
+ * 8 Lane A
+ * 9 Lane A
+ * B Lane D!
+ */
+ serdes1_0: phy@0 {
+ #phy-cells = <0>;
+ reg = <0>;
+
+ /* SGMII.6 */
+ sgmii-0 {
+ fsl,pccr = <0x8>;
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ fsl,type = <PHY_TYPE_SGMII>;
+ };
+ };
+
+ serdes1_1: phy@1 {
+ #phy-cells = <0>;
+ reg = <1>;
+
+ /* SGMII.5 */
+ sgmii-1 {
+ fsl,pccr = <0x8>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,type = <PHY_TYPE_2500BASEX>;
+ };
+ };
+
+ serdes1_2: phy@2 {
+ #phy-cells = <0>;
+ reg = <2>;
+
+ /* SGMII.10 */
+ sgmii-2 {
+ fsl,pccr = <0x8>;
+ fsl,index = <2>;
+ fsl,cfg = <0x1>;
+ fsl,type = <PHY_TYPE_2500BASEX>;
+ };
+
+ /* XFI.10 */
+ xfi-0 {
+ fsl,pccr = <0xb>;
+ fsl,index = <0>;
+ fsl,cfg = <0x2>;
+ fsl,type = <PHY_TYPE_10GBASER>;
+ };
+ };
+
+ serdes1_3: phy@3 {
+ #phy-cells = <0>;
+ reg = <3>;
+
+ /* SGMII.9 */
+ sgmii-3 {
+ fsl,pccr = <0x8>;
+ fsl,index = <3>;
+ fsl,cfg = <0x1>;
+ fsl,type = <PHY_TYPE_2500BASEX>;
+ };
+
+ /* XGI.9 */
+ xfi-9 {
+ fsl,pccr = <0xb>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ fsl,type = <PHY_TYPE_10GBASER>;
+ };
+ };
+};
+
+
&duart0 {
status = "okay";
};
@@ -140,21 +244,29 @@ ethernet@e6000 {
ethernet@e8000 {
phy-handle = <&sgmii_phy1>;
phy-connection-type = "sgmii";
+ phys = <&serdes1_1>;
+ phy-names = "serdes";
};
ethernet@ea000 {
phy-handle = <&sgmii_phy2>;
phy-connection-type = "sgmii";
+ phys = <&serdes1_0>;
+ phy-names = "serdes";
};
ethernet@f0000 { /* 10GEC1 */
phy-handle = <&aqr106_phy>;
phy-connection-type = "xgmii";
+ phys = <&serdes1_3>;
+ phy-names = "serdes";
};
ethernet@f2000 { /* 10GEC2 */
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "xgmii";
+ phys = <&serdes1_2>;
+ phy-names = "serdes";
};
mdio@fc000 {
@@ -52,6 +52,7 @@ config PHY_FSL_LYNX_10G
tristate "Freescale Layerscale Lynx 10G SerDes support"
select GENERIC_PHY
select REGMAP_MMIO
+ default y if ARCH_LAYERSCAPE
help
This adds support for the Lynx "SerDes" devices found on various QorIQ
SoCs. There may be up to four SerDes devices on each SoC, and each
This adds appropriate bindings for the macs which use the SerDes. The 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is no driver for this device (and as far as I know all you can do with the 100MHz clocks is gate them), so I have chosen to model it as a single fixed clock. Note: the SerDes1 lane numbering for the LS1046A is *reversed*. This means that Lane A (what the driver thinks is lane 0) uses pins SD1_TX3_P/N. Because this will break ethernet if the serdes is not enabled, enable the serdes driver by default on Layerscape. Signed-off-by: Sean Anderson <sean.anderson@seco.com> --- This depends on [1]. [1] https://lore.kernel.org/netdev/20220804194705.459670-4-sean.anderson@seco.com/ (no changes since v4) Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 112 ++++++++++++++++++ drivers/phy/freescale/Kconfig | 1 + 2 files changed, 113 insertions(+)