diff mbox series

[v1,1/3] gpio: rockchip: make gpio work without cru module

Message ID 20220901012944.2634398-3-jay.xu@rock-chips.com
State New
Headers show
Series gpio clock-names | expand

Commit Message

Jianqun Xu Sept. 1, 2022, 1:29 a.m. UTC
In some case the system may has no builtin cru module, the gpio driver
will fail to get periph clock and debounce clock.

On rockchip SoCs, the pclk and dbg clk are default to be enabled and
ungated, the gpio possible to work without cru module.

This patch makes gpio work fine without cru module.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
 drivers/gpio/gpio-rockchip.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

Comments

Peter Geis Sept. 2, 2022, 6:38 p.m. UTC | #1
On Wed, Aug 31, 2022 at 9:30 PM Jianqun Xu <jay.xu@rock-chips.com> wrote:
>
> In some case the system may has no builtin cru module, the gpio driver
> will fail to get periph clock and debounce clock.
>
> On rockchip SoCs, the pclk and dbg clk are default to be enabled and
> ungated, the gpio possible to work without cru module.
>
> This patch makes gpio work fine without cru module.

What happens if the cru probes later and these clocks become available
but aren't claimed so clk_disable_unused shuts them down?

>
> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> ---
>  drivers/gpio/gpio-rockchip.c | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
> index a4c4e4584f5b..1da0324445cc 100644
> --- a/drivers/gpio/gpio-rockchip.c
> +++ b/drivers/gpio/gpio-rockchip.c
> @@ -195,6 +195,9 @@ static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
>         unsigned int cur_div_reg;
>         u64 div;
>
> +       if (!bank->db_clk)
> +               return -ENOENT;
> +
>         if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
>                 div_debounce_support = true;
>                 freq = clk_get_rate(bank->db_clk);
> @@ -654,8 +657,10 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
>                 return -EINVAL;
>
>         bank->clk = of_clk_get(bank->of_node, 0);
> -       if (IS_ERR(bank->clk))
> -               return PTR_ERR(bank->clk);
> +       if (IS_ERR(bank->clk)) {
> +               bank->clk = NULL;
> +               dev_warn(bank->dev, "works without clk pm\n");
> +       }
>
>         clk_prepare_enable(bank->clk);
>         id = readl(bank->reg_base + gpio_regs_v2.version_id);
> @@ -666,9 +671,8 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
>                 bank->gpio_type = GPIO_TYPE_V2;
>                 bank->db_clk = of_clk_get(bank->of_node, 1);
>                 if (IS_ERR(bank->db_clk)) {
> -                       dev_err(bank->dev, "cannot find debounce clk\n");
> -                       clk_disable_unprepare(bank->clk);
> -                       return -EINVAL;
> +                       bank->db_clk = NULL;
> +                       dev_warn(bank->dev, "works without debounce clk pm\n");
>                 }
>         } else {
>                 bank->gpio_regs = &gpio_regs_v1;
> --
> 2.25.1
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
Heiko Stübner Sept. 2, 2022, 9:09 p.m. UTC | #2
Am Freitag, 2. September 2022, 20:38:27 CEST schrieb Peter Geis:
> On Wed, Aug 31, 2022 at 9:30 PM Jianqun Xu <jay.xu@rock-chips.com> wrote:
> >
> > In some case the system may has no builtin cru module, the gpio driver
> > will fail to get periph clock and debounce clock.
> >
> > On rockchip SoCs, the pclk and dbg clk are default to be enabled and
> > ungated, the gpio possible to work without cru module.
> >
> > This patch makes gpio work fine without cru module.
> 
> What happens if the cru probes later and these clocks become available
> but aren't claimed so clk_disable_unused shuts them down?

Also the clock controller for the soc is such a basic component, who
in their right mind would build a kernel without it and expect anything
to work.

My guess is that is simply hacking around that Android thingy with their
common kernel but vendors being allowed to move all the "special" code
to modules. We had this untested cru-module in mainline for a while
before people found out that the module part seemingly never was
tested ;-) .

The gpio driver is of course dependent on its clock supply, so hacking
around that seems really like a very bad idea.


Heiko



> 
> >
> > Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
> > ---
> >  drivers/gpio/gpio-rockchip.c | 14 +++++++++-----
> >  1 file changed, 9 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
> > index a4c4e4584f5b..1da0324445cc 100644
> > --- a/drivers/gpio/gpio-rockchip.c
> > +++ b/drivers/gpio/gpio-rockchip.c
> > @@ -195,6 +195,9 @@ static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
> >         unsigned int cur_div_reg;
> >         u64 div;
> >
> > +       if (!bank->db_clk)
> > +               return -ENOENT;
> > +
> >         if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
> >                 div_debounce_support = true;
> >                 freq = clk_get_rate(bank->db_clk);
> > @@ -654,8 +657,10 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
> >                 return -EINVAL;
> >
> >         bank->clk = of_clk_get(bank->of_node, 0);
> > -       if (IS_ERR(bank->clk))
> > -               return PTR_ERR(bank->clk);
> > +       if (IS_ERR(bank->clk)) {
> > +               bank->clk = NULL;
> > +               dev_warn(bank->dev, "works without clk pm\n");
> > +       }
> >
> >         clk_prepare_enable(bank->clk);
> >         id = readl(bank->reg_base + gpio_regs_v2.version_id);
> > @@ -666,9 +671,8 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
> >                 bank->gpio_type = GPIO_TYPE_V2;
> >                 bank->db_clk = of_clk_get(bank->of_node, 1);
> >                 if (IS_ERR(bank->db_clk)) {
> > -                       dev_err(bank->dev, "cannot find debounce clk\n");
> > -                       clk_disable_unprepare(bank->clk);
> > -                       return -EINVAL;
> > +                       bank->db_clk = NULL;
> > +                       dev_warn(bank->dev, "works without debounce clk pm\n");
> >                 }
> >         } else {
> >                 bank->gpio_regs = &gpio_regs_v1;
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > Linux-rockchip mailing list
> > Linux-rockchip@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
diff mbox series

Patch

diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index a4c4e4584f5b..1da0324445cc 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -195,6 +195,9 @@  static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
 	unsigned int cur_div_reg;
 	u64 div;
 
+	if (!bank->db_clk)
+		return -ENOENT;
+
 	if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
 		div_debounce_support = true;
 		freq = clk_get_rate(bank->db_clk);
@@ -654,8 +657,10 @@  static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
 		return -EINVAL;
 
 	bank->clk = of_clk_get(bank->of_node, 0);
-	if (IS_ERR(bank->clk))
-		return PTR_ERR(bank->clk);
+	if (IS_ERR(bank->clk)) {
+		bank->clk = NULL;
+		dev_warn(bank->dev, "works without clk pm\n");
+	}
 
 	clk_prepare_enable(bank->clk);
 	id = readl(bank->reg_base + gpio_regs_v2.version_id);
@@ -666,9 +671,8 @@  static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
 		bank->gpio_type = GPIO_TYPE_V2;
 		bank->db_clk = of_clk_get(bank->of_node, 1);
 		if (IS_ERR(bank->db_clk)) {
-			dev_err(bank->dev, "cannot find debounce clk\n");
-			clk_disable_unprepare(bank->clk);
-			return -EINVAL;
+			bank->db_clk = NULL;
+			dev_warn(bank->dev, "works without debounce clk pm\n");
 		}
 	} else {
 		bank->gpio_regs = &gpio_regs_v1;