| Message ID | 20220819231415.3860210-4-mail@conchuod.ie |
|---|---|
| State | New |
| Headers | show |
| Series | Fix RISC-V/PCI dt-schema issues with dt-schema v2022.08 | expand |
On Sat, 20 Aug 2022 00:14:12 +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The dma-ranges property was missed when adding the binding initially. > The root port can use up to 6 address translation tables, depending on > configuration. > > Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3 > Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../devicetree/bindings/pci/microchip,pcie-host.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 6fbe62f4da93..23d95c65acff 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -67,6 +67,10 @@ properties: ranges: maxItems: 1 + dma-ranges: + minItems: 1 + maxItems: 6 + msi-controller: description: Identifies the node as an MSI controller.