| Message ID | 20220815151451.23293-9-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for Renesas RZ/Five SoC | expand |
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index aed332a9d4ea..de0ccf816c08 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -26,6 +26,7 @@ CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=y CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_SOC_RENESAS_RZFIVE=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_SOC_VIRT=y @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SH_SCI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y
Enable Renesas RZ/Five SoC config in defconfig. It allows the default upstream kernel to boot on RZ/Five SMARC EVK board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- v1->v2 * New patch --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+)