| Message ID | 20220811171619.1154755-11-peter.maydell@linaro.org |
|---|---|
| State | Accepted |
| Headers | show |
| Series | target/arm: Implement FEAT_PMUv3p5 | expand |
On Thu, 11 Aug 2022 at 18:16, Peter Maydell <peter.maydell@linaro.org> wrote: > > Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5 > compliant PMU. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Oops, forgot the docs update: --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -52,6 +52,7 @@ the following architecture extensions: - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) +- FEAT_PMUv3p5 (PMU Extensions v3.5) - FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RASv1p1 (RAS Extension v1.1) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) thanks -- PMM
On 8/11/22 10:26, Peter Maydell wrote: > On Thu, 11 Aug 2022 at 18:16, Peter Maydell <peter.maydell@linaro.org> wrote: >> >> Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5 >> compliant PMU. >> >> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > > Oops, forgot the docs update: > > --- a/docs/system/arm/emulation.rst > +++ b/docs/system/arm/emulation.rst > @@ -52,6 +52,7 @@ the following architecture extensions: > - FEAT_PMULL (PMULL, PMULL2 instructions) > - FEAT_PMUv3p1 (PMU Extensions v3.1) > - FEAT_PMUv3p4 (PMU Extensions v3.4) > +- FEAT_PMUv3p5 (PMU Extensions v3.5) > - FEAT_RAS (Reliability, availability, and serviceability) > - FEAT_RASv1p1 (RAS Extension v1.1) > - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 78e27f778ac..fa4b0152706 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1072,7 +1072,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64dfr0; t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_aa64dfr0 = t; t = cpu->isar.id_aa64smfr0; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 3099b38e32b..4c71a0b612d 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -81,7 +81,7 @@ void aa32_max_features(ARMCPU *cpu) t = cpu->isar.id_dfr0; t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ + t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 = t; }
Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5 compliant PMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)