diff mbox series

dt-bindings: riscv: fix SiFive l2-cache's cache-sets

Message ID 20220803185359.942928-1-mail@conchuod.ie
State New
Headers show
Series dt-bindings: riscv: fix SiFive l2-cache's cache-sets | expand

Commit Message

Conor Dooley Aug. 3, 2022, 6:54 p.m. UTC 
From: Conor Dooley <conor.dooley@microchip.com>

Fix device tree schema validation error messages for the SiFive
Unmatched: ' cache-sets:0:0: 1024 was expected'.

The existing bindings allow for just 1024 cache-sets but the fu740 on
Unmatched the has 2048 cache-sets. The ISA itself permits any arbitrary
power of two, however this is not supported by dt-schema. The RTL for
the IP, to which the number of cache-sets is a tunable parameter, has
been released publicly so speculatively adding a small number of
"reasonable" values seems unwise also.

Instead, as the binding only supports two distinct controllers: add 2048
and explicitly lock it to the fu740's l2 cache while limiting 1024 to
the l2 cache on the fu540.

Fixes: af951c3a113b ("dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740")
Reported-by: Atul Khare <atulkhare@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
I split this off from the existing series as there is no dependancy
between this cache change and the gpio patch. The prior series can
be found at:
https://lore.kernel.org/all/20220726170725.3245278-2-mail@conchuod.ie/
---
 .../devicetree/bindings/riscv/sifive-l2-cache.yaml          | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Comments

Palmer Dabbelt Aug. 11, 2022, 9:07 p.m. UTC | #1 
On Wed, 03 Aug 2022 11:54:00 PDT (-0700), mail@conchuod.ie wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Fix device tree schema validation error messages for the SiFive
> Unmatched: ' cache-sets:0:0: 1024 was expected'.
>
> The existing bindings allow for just 1024 cache-sets but the fu740 on
> Unmatched the has 2048 cache-sets. The ISA itself permits any arbitrary
> power of two, however this is not supported by dt-schema. The RTL for
> the IP, to which the number of cache-sets is a tunable parameter, has
> been released publicly so speculatively adding a small number of
> "reasonable" values seems unwise also.
>
> Instead, as the binding only supports two distinct controllers: add 2048
> and explicitly lock it to the fu740's l2 cache while limiting 1024 to
> the l2 cache on the fu540.
>
> Fixes: af951c3a113b ("dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740")
> Reported-by: Atul Khare <atulkhare@rivosinc.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> I split this off from the existing series as there is no dependancy
> between this cache change and the gpio patch. The prior series can
> be found at:
> https://lore.kernel.org/all/20220726170725.3245278-2-mail@conchuod.ie/
> ---
>  .../devicetree/bindings/riscv/sifive-l2-cache.yaml          | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> index e2d330bd4608..69cdab18d629 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -46,7 +46,7 @@ properties:
>      const: 2
>
>    cache-sets:
> -    const: 1024
> +    enum: [1024, 2048]
>
>    cache-size:
>      const: 2097152
> @@ -84,6 +84,8 @@ then:
>        description: |
>          Must contain entries for DirError, DataError and DataFail signals.
>        maxItems: 3
> +    cache-sets:
> +      const: 1024
>
>  else:
>    properties:
> @@ -91,6 +93,8 @@ else:
>        description: |
>          Must contain entries for DirError, DataError, DataFail, DirFail signals.
>        minItems: 4
> +    cache-sets:
> +      const: 2048
>
>  additionalProperties: false

Thanks, this is on for-next.
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index e2d330bd4608..69cdab18d629 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -46,7 +46,7 @@  properties:
     const: 2
 
   cache-sets:
-    const: 1024
+    enum: [1024, 2048]
 
   cache-size:
     const: 2097152
@@ -84,6 +84,8 @@  then:
       description: |
         Must contain entries for DirError, DataError and DataFail signals.
       maxItems: 3
+    cache-sets:
+      const: 1024
 
 else:
   properties:
@@ -91,6 +93,8 @@  else:
       description: |
         Must contain entries for DirError, DataError, DataFail, DirFail signals.
       minItems: 4
+    cache-sets:
+      const: 2048
 
 additionalProperties: false