| Message ID | 20220725131521.607904-2-robert.marko@sartura.hr |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 38da24c1796c..ea2b07ca2887 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -40,14 +40,16 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; - enable-method = "psci"; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x0000fff8>; next-level-cache = <&L2_0>; }; L2_0: l2-cache0 {
As described in previous commit, PSCI is not implemented on this SoC at all, so use spin-tables to bringup the cores. Tested on PCB134 with eMMC (VSC5640EV). Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)