| Message ID | 20220709142006.836754-1-Perry.Yuan@amd.com |
|---|---|
| State | Superseded |
| Headers | show
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From: Perry Yuan <Perry.Yuan@amd.com>
To: <rafael.j.wysocki@intel.com>, <viresh.kumar@linaro.org>,
<Ray.Huang@amd.com>
CC: <Deepak.Sharma@amd.com>, <Mario.Limonciello@amd.com>,
<Nathan.Fontenot@amd.com>, <Alexander.Deucher@amd.com>,
<Jinzhou.Su@amd.com>, <Xinmei.Huang@amd.com>,
<Xiaojian.Du@amd.com>, <Li.Meng@amd.com>,
<linux-pm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Perry Yuan <Perry.Yuan@amd.com>
Subject: [PATCH v2 12/14] cpufreq: amd_pstate: update transition delay time to
1ms
Date: Sat, 9 Jul 2022 10:20:06 -0400
Message-ID: <20220709142006.836754-1-Perry.Yuan@amd.com>
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| Series |
[v2,01/14] x86/msr: Add the MSR definition for AMD CPPC hardware control.
|
expand
|
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 4c600cd7cb5b..8ba4b98b7108 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -42,7 +42,7 @@ #include "amd-pstate-trace.h" #define AMD_PSTATE_TRANSITION_LATENCY 20000 -#define AMD_PSTATE_TRANSITION_DELAY 500 +#define AMD_PSTATE_TRANSITION_DELAY 1000 /* * TODO: We need more time to fine tune processors with shared memory solution