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[04/12] i2c: xiic: Add wait for FIFO empty in send_tx

Message ID 1656072327-13628-5-git-send-email-manikanta.guntupalli@xilinx.com
State New
Headers show
Series i2c: xiic: Added Standard mode and SMBus | expand

Commit Message

Manikanta Guntupalli June 24, 2022, 12:05 p.m. UTC 
From: Raviteja Narayanam <raviteja.narayanam@xilinx.com>

If the tx_half_empty interrupt comes first instead of tx_empty,
STOP bit is generated even before all the bytes are transmitted
out on the bus.
STOP bit should be sent only after all the bytes in the FIFO are
transmitted out of the FIFO. So wait until FIFO is empty before sending
the STOP bit.

Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@xilinx.com>
---
 drivers/i2c/busses/i2c-xiic.c | 6 ++++++
 1 file changed, 6 insertions(+)
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Patch

diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 2d5214f1ba03..9c3266ac209e 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -472,6 +472,12 @@  static void xiic_send_tx(struct xiic_i2c *i2c)
 
 		if (i2c->nmsgs == 1) {
 			u8 cr;
+			int status;
+
+			/* Wait till FIFO is empty so STOP is sent last */
+			status = xiic_wait_tx_empty(i2c);
+			if (status)
+				return;
 
 			/* Write to CR to stop */
 			cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);