@@ -399,8 +399,16 @@ static int micron_st_nor_ready(struct spi_nor *nor)
return sr_ready;
ret = micron_st_nor_read_fsr(nor, nor->bouncebuf);
- if (ret)
- return ret;
+ if (ret < 0) {
+ /*
+ * Some controllers, such as Intel SPI, do not support low
+ * level operations such as reading the flag status
+ * register. They only expose small amount of high level
+ * operations to the software. If this is the case we use
+ * only the status register value.
+ */
+ return (ret == -ENOTSUPP || ret == -EOPNOTSUPP) ? sr_ready : ret;
+ }
if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
if (nor->bouncebuf[0] & FSR_E_ERR)
@@ -352,7 +352,8 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)
val |= HSFSTS_CTL_FCYCLE_RDSR;
break;
default:
- return -EINVAL;
+ dev_dbg(ispi->dev, "%#x not supported\n", opcode);
+ return -EOPNOTSUPP;
}
if (len > INTEL_SPI_FIFO_SZ)