| Message ID | 20220619212549.1240891-5-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml | expand |
On 19.06.2022 23:25, Dmitry Baryshkov wrote: > Move clock parent tables down, after the GPLL declrataions, so that we > can use gpll hw clock fields in the next commit. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > drivers/clk/qcom/gcc-msm8916.c | 216 ++++++++++++++++----------------- > 1 file changed, 108 insertions(+), 108 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c > index 40c27ba6286f..7962edbdbcf6 100644 > --- a/drivers/clk/qcom/gcc-msm8916.c > +++ b/drivers/clk/qcom/gcc-msm8916.c > @@ -42,6 +42,114 @@ enum { > P_EXT_MCLK, > }; > > +static struct clk_pll gpll0 = { > + .l_reg = 0x21004, > + .m_reg = 0x21008, > + .n_reg = 0x2100c, > + .config_reg = 0x21010, > + .mode_reg = 0x21000, > + .status_reg = 0x2101c, > + .status_bit = 17, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpll0", > + .parent_names = (const char *[]){ "xo" }, > + .num_parents = 1, > + .ops = &clk_pll_ops, > + }, > +}; > + > +static struct clk_regmap gpll0_vote = { > + .enable_reg = 0x45000, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpll0_vote", > + .parent_names = (const char *[]){ "gpll0" }, > + .num_parents = 1, > + .ops = &clk_pll_vote_ops, > + }, > +}; > + > +static struct clk_pll gpll1 = { > + .l_reg = 0x20004, > + .m_reg = 0x20008, > + .n_reg = 0x2000c, > + .config_reg = 0x20010, > + .mode_reg = 0x20000, > + .status_reg = 0x2001c, > + .status_bit = 17, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpll1", > + .parent_names = (const char *[]){ "xo" }, > + .num_parents = 1, > + .ops = &clk_pll_ops, > + }, > +}; > + > +static struct clk_regmap gpll1_vote = { > + .enable_reg = 0x45000, > + .enable_mask = BIT(1), > + .hw.init = &(struct clk_init_data){ > + .name = "gpll1_vote", > + .parent_names = (const char *[]){ "gpll1" }, > + .num_parents = 1, > + .ops = &clk_pll_vote_ops, > + }, > +}; > + > +static struct clk_pll gpll2 = { > + .l_reg = 0x4a004, > + .m_reg = 0x4a008, > + .n_reg = 0x4a00c, > + .config_reg = 0x4a010, > + .mode_reg = 0x4a000, > + .status_reg = 0x4a01c, > + .status_bit = 17, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpll2", > + .parent_names = (const char *[]){ "xo" }, > + .num_parents = 1, > + .ops = &clk_pll_ops, > + }, > +}; > + > +static struct clk_regmap gpll2_vote = { > + .enable_reg = 0x45000, > + .enable_mask = BIT(2), > + .hw.init = &(struct clk_init_data){ > + .name = "gpll2_vote", > + .parent_names = (const char *[]){ "gpll2" }, > + .num_parents = 1, > + .ops = &clk_pll_vote_ops, > + }, > +}; > + > +static struct clk_pll bimc_pll = { > + .l_reg = 0x23004, > + .m_reg = 0x23008, > + .n_reg = 0x2300c, > + .config_reg = 0x23010, > + .mode_reg = 0x23000, > + .status_reg = 0x2301c, > + .status_bit = 17, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "bimc_pll", > + .parent_names = (const char *[]){ "xo" }, > + .num_parents = 1, > + .ops = &clk_pll_ops, > + }, > +}; > + > +static struct clk_regmap bimc_pll_vote = { > + .enable_reg = 0x45000, > + .enable_mask = BIT(3), > + .hw.init = &(struct clk_init_data){ > + .name = "bimc_pll_vote", > + .parent_names = (const char *[]){ "bimc_pll" }, > + .num_parents = 1, > + .ops = &clk_pll_vote_ops, > + }, > +}; > + > static const struct parent_map gcc_xo_gpll0_map[] = { > { P_XO, 0 }, > { P_GPLL0, 1 }, > @@ -256,114 +364,6 @@ static const char * const gcc_xo_gpll1_emclk_sleep[] = { > "sleep_clk", > }; > > -static struct clk_pll gpll0 = { > - .l_reg = 0x21004, > - .m_reg = 0x21008, > - .n_reg = 0x2100c, > - .config_reg = 0x21010, > - .mode_reg = 0x21000, > - .status_reg = 0x2101c, > - .status_bit = 17, > - .clkr.hw.init = &(struct clk_init_data){ > - .name = "gpll0", > - .parent_names = (const char *[]){ "xo" }, > - .num_parents = 1, > - .ops = &clk_pll_ops, > - }, > -}; > - > -static struct clk_regmap gpll0_vote = { > - .enable_reg = 0x45000, > - .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data){ > - .name = "gpll0_vote", > - .parent_names = (const char *[]){ "gpll0" }, > - .num_parents = 1, > - .ops = &clk_pll_vote_ops, > - }, > -}; > - > -static struct clk_pll gpll1 = { > - .l_reg = 0x20004, > - .m_reg = 0x20008, > - .n_reg = 0x2000c, > - .config_reg = 0x20010, > - .mode_reg = 0x20000, > - .status_reg = 0x2001c, > - .status_bit = 17, > - .clkr.hw.init = &(struct clk_init_data){ > - .name = "gpll1", > - .parent_names = (const char *[]){ "xo" }, > - .num_parents = 1, > - .ops = &clk_pll_ops, > - }, > -}; > - > -static struct clk_regmap gpll1_vote = { > - .enable_reg = 0x45000, > - .enable_mask = BIT(1), > - .hw.init = &(struct clk_init_data){ > - .name = "gpll1_vote", > - .parent_names = (const char *[]){ "gpll1" }, > - .num_parents = 1, > - .ops = &clk_pll_vote_ops, > - }, > -}; > - > -static struct clk_pll gpll2 = { > - .l_reg = 0x4a004, > - .m_reg = 0x4a008, > - .n_reg = 0x4a00c, > - .config_reg = 0x4a010, > - .mode_reg = 0x4a000, > - .status_reg = 0x4a01c, > - .status_bit = 17, > - .clkr.hw.init = &(struct clk_init_data){ > - .name = "gpll2", > - .parent_names = (const char *[]){ "xo" }, > - .num_parents = 1, > - .ops = &clk_pll_ops, > - }, > -}; > - > -static struct clk_regmap gpll2_vote = { > - .enable_reg = 0x45000, > - .enable_mask = BIT(2), > - .hw.init = &(struct clk_init_data){ > - .name = "gpll2_vote", > - .parent_names = (const char *[]){ "gpll2" }, > - .num_parents = 1, > - .ops = &clk_pll_vote_ops, > - }, > -}; > - > -static struct clk_pll bimc_pll = { > - .l_reg = 0x23004, > - .m_reg = 0x23008, > - .n_reg = 0x2300c, > - .config_reg = 0x23010, > - .mode_reg = 0x23000, > - .status_reg = 0x2301c, > - .status_bit = 17, > - .clkr.hw.init = &(struct clk_init_data){ > - .name = "bimc_pll", > - .parent_names = (const char *[]){ "xo" }, > - .num_parents = 1, > - .ops = &clk_pll_ops, > - }, > -}; > - > -static struct clk_regmap bimc_pll_vote = { > - .enable_reg = 0x45000, > - .enable_mask = BIT(3), > - .hw.init = &(struct clk_init_data){ > - .name = "bimc_pll_vote", > - .parent_names = (const char *[]){ "bimc_pll" }, > - .num_parents = 1, > - .ops = &clk_pll_vote_ops, > - }, > -}; > - > static struct clk_rcg2 pcnoc_bfdcd_clk_src = { > .cmd_rcgr = 0x27000, > .hid_width = 5,
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 40c27ba6286f..7962edbdbcf6 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -42,6 +42,114 @@ enum { P_EXT_MCLK, }; +static struct clk_pll gpll0 = { + .l_reg = 0x21004, + .m_reg = 0x21008, + .n_reg = 0x2100c, + .config_reg = 0x21010, + .mode_reg = 0x21000, + .status_reg = 0x2101c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll0_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_vote", + .parent_names = (const char *[]){ "gpll0" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll1 = { + .l_reg = 0x20004, + .m_reg = 0x20008, + .n_reg = 0x2000c, + .config_reg = 0x20010, + .mode_reg = 0x20000, + .status_reg = 0x2001c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll1", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll1_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_vote", + .parent_names = (const char *[]){ "gpll1" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll2 = { + .l_reg = 0x4a004, + .m_reg = 0x4a008, + .n_reg = 0x4a00c, + .config_reg = 0x4a010, + .mode_reg = 0x4a000, + .status_reg = 0x4a01c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll2", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll2_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gpll2_vote", + .parent_names = (const char *[]){ "gpll2" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll bimc_pll = { + .l_reg = 0x23004, + .m_reg = 0x23008, + .n_reg = 0x2300c, + .config_reg = 0x23010, + .mode_reg = 0x23000, + .status_reg = 0x2301c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "bimc_pll", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap bimc_pll_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "bimc_pll_vote", + .parent_names = (const char *[]){ "bimc_pll" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + static const struct parent_map gcc_xo_gpll0_map[] = { { P_XO, 0 }, { P_GPLL0, 1 }, @@ -256,114 +364,6 @@ static const char * const gcc_xo_gpll1_emclk_sleep[] = { "sleep_clk", }; -static struct clk_pll gpll0 = { - .l_reg = 0x21004, - .m_reg = 0x21008, - .n_reg = 0x2100c, - .config_reg = 0x21010, - .mode_reg = 0x21000, - .status_reg = 0x2101c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll0_vote = { - .enable_reg = 0x45000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_vote", - .parent_names = (const char *[]){ "gpll0" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll gpll1 = { - .l_reg = 0x20004, - .m_reg = 0x20008, - .n_reg = 0x2000c, - .config_reg = 0x20010, - .mode_reg = 0x20000, - .status_reg = 0x2001c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll1", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll1_vote = { - .enable_reg = 0x45000, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gpll1_vote", - .parent_names = (const char *[]){ "gpll1" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll gpll2 = { - .l_reg = 0x4a004, - .m_reg = 0x4a008, - .n_reg = 0x4a00c, - .config_reg = 0x4a010, - .mode_reg = 0x4a000, - .status_reg = 0x4a01c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll2", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll2_vote = { - .enable_reg = 0x45000, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gpll2_vote", - .parent_names = (const char *[]){ "gpll2" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll bimc_pll = { - .l_reg = 0x23004, - .m_reg = 0x23008, - .n_reg = 0x2300c, - .config_reg = 0x23010, - .mode_reg = 0x23000, - .status_reg = 0x2301c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "bimc_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap bimc_pll_vote = { - .enable_reg = 0x45000, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "bimc_pll_vote", - .parent_names = (const char *[]){ "bimc_pll" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static struct clk_rcg2 pcnoc_bfdcd_clk_src = { .cmd_rcgr = 0x27000, .hid_width = 5,
Move clock parent tables down, after the GPLL declrataions, so that we can use gpll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-msm8916.c | 216 ++++++++++++++++----------------- 1 file changed, 108 insertions(+), 108 deletions(-)