diff mbox

[v6,11/21] KVM: ARM64: Add access handler for PMXEVCNTR register

Message ID 1449578860-15808-12-git-send-email-zhaoshenglong@huawei.com
State New
Headers show

Commit Message

Shannon Zhao Dec. 8, 2015, 12:47 p.m. UTC 
From: Shannon Zhao <shannon.zhao@linaro.org>


Accessing PMXEVCNTR register is mapped to the PMEVCNTRn or PMCCNTR which
is selected by PMSELR.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>

---
 arch/arm64/kvm/sys_regs.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 42 insertions(+), 2 deletions(-)

-- 
2.0.4



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diff mbox

Patch

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f7a73b5..2304937 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -516,6 +516,46 @@  out:
 	return true;
 }
 
+static bool access_pmu_pmxevcntr(struct kvm_vcpu *vcpu,
+				 struct sys_reg_params *p,
+				 const struct sys_reg_desc *r)
+{
+	u64 pmcr, idx, val;
+
+	if (!vcpu_mode_is_32bit(vcpu)) {
+		pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
+		idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+
+		if (!pmu_counter_idx_valid(pmcr, idx))
+			goto out;
+
+		val = kvm_pmu_get_counter_value(vcpu, idx);
+		if (!p->is_write) {
+			p->regval = val;
+			goto out;
+		}
+
+		vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + idx) += (s64)p->regval - val;
+	} else {
+		pmcr = vcpu_cp15(vcpu, c9_PMCR);
+		idx = vcpu_cp15(vcpu, c9_PMSELR) & ARMV8_COUNTER_MASK;
+
+		if (!pmu_counter_idx_valid(pmcr, idx))
+			goto out;
+
+		val = kvm_pmu_get_counter_value(vcpu, idx);
+		if (!p->is_write) {
+			p->regval = val;
+			goto out;
+		}
+
+		vcpu_cp15(vcpu, c14_PMEVCNTR0 + idx) += (s64)p->regval - val;
+	}
+
+out:
+	return true;
+}
+
 /* PMU registers accessor. */
 static bool access_pmu_regs(struct kvm_vcpu *vcpu,
 			    struct sys_reg_params *p,
@@ -804,7 +844,7 @@  static const struct sys_reg_desc sys_reg_descs[] = {
 	  access_pmu_pmxevtyper },
 	/* PMXEVCNTR_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
-	  trap_raz_wi },
+	  access_pmu_pmxevcntr },
 	/* PMUSERENR_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
 	  trap_raz_wi },
@@ -1192,7 +1232,7 @@  static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_cp15_regs,
 	  NULL, c9_PMCCNTR },
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_pmxevtyper },
-	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
+	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_pmxevcntr },
 	{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },