| Message ID | 20220602214853.496211-22-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Scalable Matrix Extension | expand |
On Thu, 2 Jun 2022 at 23:11, Richard Henderson <richard.henderson@linaro.org> wrote: > > This register is part of SME, but isn't closely related to the > rest of the extension. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 1 + > target/arm/helper.c | 32 ++++++++++++++++++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 24c5266f35..245d144fa1 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -474,6 +474,7 @@ typedef struct CPUArchState { > }; > uint64_t tpidr_el[4]; > }; > + uint64_t tpidr2_el0; > /* The secure banks of these registers don't map anywhere */ > uint64_t tpidrurw_s; > uint64_t tpidrprw_s; > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 48534db0bd..204c5cf849 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6283,6 +6283,35 @@ static const ARMCPRegInfo zcr_reginfo[] = { > .writefn = zcr_write, .raw_writefn = raw_write }, > }; > > +#ifdef TARGET_AARCH64 > +static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, > + bool isread) > +{ > + int el = arm_current_el(env); > + > + if (el == 0) { > + uint64_t sctlr = arm_sctlr(env, el); > + if (!(sctlr & SCTLR_EnTP2)) { > + uint64_t hcr = arm_hcr_el2_eff(env); > + return hcr & HCR_TGE ? CP_ACCESS_TRAP_EL2 : CP_ACCESS_TRAP; Do we really need to do this rather than just returning CP_ACCESS_TRAP and letting the "take trap to EL2 if TGE enabled" check in raise_exception() do the TGE routing? > + } > + } > + if (el < 3 > + && arm_feature(env, ARM_FEATURE_EL3) > + && !(env->cp15.scr_el3 & SCR_ENTP2)) { > + return CP_ACCESS_TRAP_EL3; > + } > + return CP_ACCESS_OK; > +} thanks -- PMM
On 6/6/22 06:18, Peter Maydell wrote: >> + if (!(sctlr & SCTLR_EnTP2)) { >> + uint64_t hcr = arm_hcr_el2_eff(env); >> + return hcr & HCR_TGE ? CP_ACCESS_TRAP_EL2 : CP_ACCESS_TRAP; > > Do we really need to do this rather than just returning > CP_ACCESS_TRAP and letting the "take trap to EL2 if TGE > enabled" check in raise_exception() do the TGE routing? No, you're right. r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 24c5266f35..245d144fa1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -474,6 +474,7 @@ typedef struct CPUArchState { }; uint64_t tpidr_el[4]; }; + uint64_t tpidr2_el0; /* The secure banks of these registers don't map anywhere */ uint64_t tpidrurw_s; uint64_t tpidrprw_s; diff --git a/target/arm/helper.c b/target/arm/helper.c index 48534db0bd..204c5cf849 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6283,6 +6283,35 @@ static const ARMCPRegInfo zcr_reginfo[] = { .writefn = zcr_write, .raw_writefn = raw_write }, }; +#ifdef TARGET_AARCH64 +static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el == 0) { + uint64_t sctlr = arm_sctlr(env, el); + if (!(sctlr & SCTLR_EnTP2)) { + uint64_t hcr = arm_hcr_el2_eff(env); + return hcr & HCR_TGE ? CP_ACCESS_TRAP_EL2 : CP_ACCESS_TRAP; + } + } + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENTP2)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo sme_reginfo[] = { + { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, + .access = PL0_RW, .accessfn = access_tpidr2, + .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, +}; +#endif /* TARGET_AARCH64 */ + void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env = &cpu->env; @@ -8444,6 +8473,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } #ifdef TARGET_AARCH64 + if (cpu_isar_feature(aa64_sme, cpu)) { + define_arm_cp_regs(cpu, sme_reginfo); + } if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); }
This register is part of SME, but isn't closely related to the rest of the extension. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 1 + target/arm/helper.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+)