| Message ID | 20220531114258.855804-1-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Declare support for FEAT_RASv1p1 | expand |
On 5/31/22 04:42, Peter Maydell wrote: > The architectural feature RASv1p1 introduces the following new > features: > * new registers ERXPFGCDN_EL1, ERXPFGCTL_EL1 and ERXPFGF_EL1 > * new bits in the fine-grained trap registers that control traps > for these new registers > * new trap bits HCR_EL2.FIEN and SCR_EL3.FIEN that control traps > for ERXPFGCDN_EL1, ERXPFGCTL_EL1, ERXPFGP_EL1 > * a larger number of the ERXMISC<n>_EL1 registers > * the format of ERR<n>STATUS registers changes > > The architecture permits that if ERRIDR_EL1.NUM is 0 (as it is for > QEMU) then all these new registers may UNDEF, and the HCR_EL2.FIEN > and SCR_EL3.FIEN bits may be RES0. We don't have any ERR<n>STATUS > registers (again, because ERRIDR_EL1.NUM is 0). QEMU does not yet > implement the fine-grained-trap extension. So there is nothing we > need to implement to be compliant with the feature spec. Make the > 'max' CPU report the feature in its ID registers, and document it. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 49cc3e8340e..81467f02ce9 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -52,6 +52,7 @@ the following architecture extensions: - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) - FEAT_RAS (Reliability, availability, and serviceability) +- FEAT_RASv1p1 (RAS Extension v1.1) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) - FEAT_RNG (Random number generator) - FEAT_S2FWB (Stage 2 forced Write-Back) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3ff9219ca3b..bd1c62a3428 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -916,6 +916,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=on property. */ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 1); /* FEAT_RASv1p1 */ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 = t;
The architectural feature RASv1p1 introduces the following new features: * new registers ERXPFGCDN_EL1, ERXPFGCTL_EL1 and ERXPFGF_EL1 * new bits in the fine-grained trap registers that control traps for these new registers * new trap bits HCR_EL2.FIEN and SCR_EL3.FIEN that control traps for ERXPFGCDN_EL1, ERXPFGCTL_EL1, ERXPFGP_EL1 * a larger number of the ERXMISC<n>_EL1 registers * the format of ERR<n>STATUS registers changes The architecture permits that if ERRIDR_EL1.NUM is 0 (as it is for QEMU) then all these new registers may UNDEF, and the HCR_EL2.FIEN and SCR_EL3.FIEN bits may be RES0. We don't have any ERR<n>STATUS registers (again, because ERRIDR_EL1.NUM is 0). QEMU does not yet implement the fine-grained-trap extension. So there is nothing we need to implement to be compliant with the feature spec. Make the 'max' CPU report the feature in its ID registers, and document it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+)