[016/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_data

Message ID	20220527181907.189259-17-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 016/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_data Date: Fri, 27 May 2022 11:17:29 -0700 Message-Id: <20220527181907.189259-17-richard.henderson@linaro.org> In-Reply-To: <20220527181907.189259-1-richard.henderson@linaro.org> References: <20220527181907.189259-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Rewrite sve feature tests \| expand [000/114] target/arm: Rewrite sve feature tests [001/114] target/arm: Introduce TRANS, TRANS_FEAT [002/114] target/arm: Move null function and sve check into gen_gvec_ool_zz [003/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_zz [004/114] target/arm: Move null function and sve check into gen_gvec_ool_zzz [005/114] target/arm: Introduce gen_gvec_ool_arg_zzz [006/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz [007/114] target/arm: Use TRANS_FEAT for do_sve2_zzz_ool [008/114] target/arm: Move null function and sve check into gen_gvec_ool_zzzz [009/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz [010/114] target/arm: Introduce gen_gvec_ool_arg_zzzz [011/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool [012/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz [013/114] target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz [014/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzxz [015/114] target/arm: Use TRANS_FEAT for do_sve2_zzz_data [016/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_data [017/114] target/arm: Use TRANS_FEAT for do_sve2_zzw_data [018/114] target/arm: Use TRANS_FEAT for USDOT_zzzz [019/114] target/arm: Move null function and sve check into gen_gvec_ool_zzp [020/114] target/arm: Introduce gen_gvec_ool_arg_zpz [021/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz [022/114] target/arm: Use TRANS_FEAT for do_sve2_zpz_data [023/114] target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi [024/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzi [025/114] target/arm: Move null function and sve check into gen_gvec_ool_zzzp [026/114] target/arm: Introduce gen_gvec_ool_arg_zpzz [027/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz [028/114] target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool [029/114] target/arm: Merge gen_gvec_fn_zz into do_mov_z [030/114] target/arm: Move null function and sve check into gen_gvec_fn_zzz [031/114] target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz [032/114] target/arm: More use of gen_gvec_fn_arg_zzz [033/114] target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz [034/114] target/arm: Use TRANS_FEAT for do_sve2_fn_zzz [035/114] target/arm: Use TRANS_FEAT for RAX1 [036/114] target/arm: Introduce gen_gvec_fn_arg_zzzz [037/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn [038/114] target/arm: Introduce gen_gvec_fn_zzi [039/114] target/arm: Use TRANS_FEAT for do_zz_dbm [040/114] target/arm: Hoist sve access check through do_sel_z [041/114] target/arm: Introduce gen_gvec_fn_arg_zzi [042/114] target/arm: Use TRANS_FEAT for do_sve2_fn2i [043/114] target/arm: Use TRANS_FEAT for do_vpz_ool [044/114] target/arm: Use TRANS_FEAT for do_shift_imm [045/114] target/arm: Introduce do_shift_zpzi [046/114] target/arm: Use TRANS_FEAT for do_shift_zpzi [047/114] target/arm: Use TRANS_FEAT for do_zpzzz_ool [048/114] target/arm: Move sve check into do_index [049/114] target/arm: Use TRANS_FEAT for do_index [050/114] target/arm: Use TRANS_FEAT for do_adr [051/114] target/arm: Use TRANS_FEAT for do_predset [052/114] target/arm: Use TRANS_FEAT for RDFFR, WRFFR [053/114] target/arm: Use TRANS_FEAT for do_pfirst_pnext [054/114] target/arm: Use TRANS_FEAT for do_EXT [055/114] target/arm: Use TRANS_FEAT for do_perm_pred3 [056/114] target/arm: Use TRANS_FEAT for do_perm_pred2 [057/114] target/arm: Move sve zip high_ofs into simd_data [058/114] target/arm: Use gen_gvec_ool_arg_zzz for do_zip, do_zip_q [059/114] target/arm: Use TRANS_FEAT for do_zip, do_zip_q [060/114] target/arm: Use TRANS_FEAT for do_clast_vector [061/114] target/arm: Use TRANS_FEAT for do_clast_fp [062/114] target/arm: Use TRANS_FEAT for do_clast_general [063/114] target/arm: Use TRANS_FEAT for do_last_fp [064/114] target/arm: Use TRANS_FEAT for do_last_general [065/114] target/arm: Use TRANS_FEAT for SPLICE [066/114] target/arm: Use TRANS_FEAT for do_ppzz_flags [067/114] target/arm: Use TRANS_FEAT for do_sve2_ppzz_flags [068/114] target/arm: Use TRANS_FEAT for do_ppzi_flags [069/114] target/arm: Use TRANS_FEAT for do_brk2, do_brk3 [070/114] target/arm: Use TRANS_FEAT for MUL_zzi [071/114] target/arm: Reject dup_i w/ shifted byte early [072/114] target/arm: Reject add/sub w/ shifted byte early [073/114] target/arm: Reject copy w/ shifted byte early [074/114] target/arm: Use TRANS_FEAT for ADD_zzi [075/114] target/arm: Use TRANS_FEAT for do_zzi_sat [076/114] target/arm: Use TRANS_FEAT for do_zzi_ool [077/114] target/arm: Introduce gen_gvec_{ptr,fpst}_zzzz [078/114] target/arm: Use TRANS_FEAT for FMMLA [079/114] target/arm: Move sve check into gen_gvec_fn_ppp [080/114] target/arm: Implement NOT (prediates) alias [081/114] target/arm: Use TRANS_FEAT for SEL_zpzz [082/114] target/arm: Use TRANS_FEAT for MOVPRFX [083/114] target/arm: Use TRANS_FEAT for FMLA [084/114] target/arm: Use TRANS_FEAT for BFMLA [085/114] target/arm: Rename do_zzz_fp to gen_gvec_ool_fpst_arg_zzz [086/114] target/arm: Use TRANS_FEAT for DO_FP3 [087/114] target/arm: Use TRANS_FEAT for FMUL_zzx [088/114] target/arm: Use TRANS_FEAT for FTMAD [089/114] target/arm: Move null function and sve check into do_reduce [090/114] target/arm: Use TRANS_FEAT for do_reduce [091/114] target/arm: Use TRANS_FEAT for FRECPE, FRSQRTE [092/114] target/arm: Expand frint_fns for MO_8 [093/114] target/arm: Rename do_zpz_ptr to gen_gvec_ool_fpst_arg_zpz [094/114] target/arm: Move null function and sve check into do_frint_mode [095/114] target/arm: Use TRANS_FEAT for do_frint_mode [096/114] target/arm: Use TRANS_FEAT for FLOGB [097/114] target/arm: Use TRANS_FEAT for do_ppz_fp [098/114] target/arm: Rename do_zpzz_ptr to gen_gvec_fpst_arg_zpzz [099/114] target/arm: Use TRANS_FEAT for gen_gvec_fpst_arg_zpzz [100/114] target/arm: Use TRANS_FEAT for FCADD [101/114] target/arm: Introduce gen_gvec_fpst_zzzzp [102/114] target/arm: Use TRANS_FEAT for gen_gvec_fpst_zzzzp [103/114] target/arm: Move null function and sve check into do_fp_imm [104/114] target/arm: Use TRANS_FEAT for DO_FP_IMM [105/114] target/arm: Use TRANS_FEAT for DO_FPCMP [106/114] target/arm: Remove assert in trans_FCMLA_zzxz [107/114] target/arm: Use TRANS_FEAT for FCMLA_zzxz [108/114] target/arm: Use TRANS_FEAT for do_narrow_extract [109/114] target/arm: Use TRANS_FEAT for do_shll_tb [110/114] target/arm: Use TRANS_FEAT for do_shr_narrow [111/114] target/arm: Use TRANS_FEAT for do_FMLAL_zzzw [112/114] target/arm: Use TRANS_FEAT for do_FMLAL_zzxw [113/114] target/arm: Add sve feature check for remaining trans_* functions [114/114] target/arm: Remove aa64_sve check from before disas_sve

Message ID

20220527181907.189259-17-richard.henderson@linaro.org

State

New

Headers

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 016/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_data
Date: Fri, 27 May 2022 11:17:29 -0700
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Series

target/arm: Rewrite sve feature tests | expand

Commit Message

Richard Henderson May 27, 2022, 6:17 p.m. UTC

Convert SVE translation functions using do_sve2_zzzz_data
to use TRANS_FEAT and gen_gvec_ool_{zzzz,zzxz}.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-sve.c | 106 ++++++++++++++-----------------------
 1 file changed, 41 insertions(+), 65 deletions(-)

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index ac76705da6..c345399ace 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3879,90 +3879,66 @@  DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
 
 #undef DO_SVE2_RRX_TB
 
-static bool do_sve2_zzzz_data(DisasContext *s, int rd, int rn, int rm, int ra,
-                              int data, gen_helper_gvec_4 *fn)
-{
-    if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
-        return false;
-    }
-    if (sve_access_check(s)) {
-        unsigned vsz = vec_full_reg_size(s);
-        tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
-                           vec_full_reg_offset(s, rn),
-                           vec_full_reg_offset(s, rm),
-                           vec_full_reg_offset(s, ra),
-                           vsz, vsz, data, fn);
-    }
-    return true;
-}
-
 #define DO_SVE2_RRXR(NAME, FUNC) \
-    static bool NAME(DisasContext *s, arg_rrxr_esz *a)  \
-    { return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra, a->index, FUNC); }
+    TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a)
 
-DO_SVE2_RRXR(trans_MLA_zzxz_h, gen_helper_gvec_mla_idx_h)
-DO_SVE2_RRXR(trans_MLA_zzxz_s, gen_helper_gvec_mla_idx_s)
-DO_SVE2_RRXR(trans_MLA_zzxz_d, gen_helper_gvec_mla_idx_d)
+DO_SVE2_RRXR(MLA_zzxz_h, gen_helper_gvec_mla_idx_h)
+DO_SVE2_RRXR(MLA_zzxz_s, gen_helper_gvec_mla_idx_s)
+DO_SVE2_RRXR(MLA_zzxz_d, gen_helper_gvec_mla_idx_d)
 
-DO_SVE2_RRXR(trans_MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
-DO_SVE2_RRXR(trans_MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
-DO_SVE2_RRXR(trans_MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
+DO_SVE2_RRXR(MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
+DO_SVE2_RRXR(MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
+DO_SVE2_RRXR(MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
 
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h)
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s)
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d)
+DO_SVE2_RRXR(SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h)
+DO_SVE2_RRXR(SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s)
+DO_SVE2_RRXR(SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d)
 
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h)
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s)
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d)
+DO_SVE2_RRXR(SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h)
+DO_SVE2_RRXR(SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s)
+DO_SVE2_RRXR(SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d)
 
 #undef DO_SVE2_RRXR
 
 #define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \
-    static bool NAME(DisasContext *s, arg_rrxr_esz *a)          \
-    {                                                           \
-        return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->rd, \
-                                 (a->index << 1) | TOP, FUNC);  \
-    }
+    TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC,        \
+               a->rd, a->rn, a->rm, a->ra, (a->index << 1) | TOP)
 
-DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false)
-DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false)
-DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true)
-DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true)
+DO_SVE2_RRXR_TB(SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false)
+DO_SVE2_RRXR_TB(SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false)
+DO_SVE2_RRXR_TB(SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true)
+DO_SVE2_RRXR_TB(SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true)
 
-DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false)
-DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false)
-DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true)
-DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true)
+DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false)
+DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false)
+DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true)
+DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true)
 
-DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false)
-DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false)
-DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true)
-DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true)
+DO_SVE2_RRXR_TB(SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false)
+DO_SVE2_RRXR_TB(SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false)
+DO_SVE2_RRXR_TB(SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true)
+DO_SVE2_RRXR_TB(SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true)
 
-DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false)
-DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false)
-DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true)
-DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true)
+DO_SVE2_RRXR_TB(UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false)
+DO_SVE2_RRXR_TB(UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false)
+DO_SVE2_RRXR_TB(UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true)
+DO_SVE2_RRXR_TB(UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true)
 
-DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false)
-DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false)
-DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true)
-DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true)
+DO_SVE2_RRXR_TB(SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false)
+DO_SVE2_RRXR_TB(SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false)
+DO_SVE2_RRXR_TB(SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true)
+DO_SVE2_RRXR_TB(SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true)
 
-DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false)
-DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false)
-DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true)
-DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true)
+DO_SVE2_RRXR_TB(UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false)
+DO_SVE2_RRXR_TB(UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false)
+DO_SVE2_RRXR_TB(UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true)
+DO_SVE2_RRXR_TB(UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true)
 
 #undef DO_SVE2_RRXR_TB
 
 #define DO_SVE2_RRXR_ROT(NAME, FUNC) \
-    static bool trans_##NAME(DisasContext *s, arg_##NAME *a)       \
-    {                                                              \
-        return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra,    \
-                                 (a->index << 2) | a->rot, FUNC);  \
-    }
+    TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC,           \
+               a->rd, a->rn, a->rm, a->ra, (a->index << 2) | a->rot)
 
 DO_SVE2_RRXR_ROT(CMLA_zzxz_h, gen_helper_sve2_cmla_idx_h)
 DO_SVE2_RRXR_ROT(CMLA_zzxz_s, gen_helper_sve2_cmla_idx_s)

[016/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_data

Commit Message

Patch